Sr.Staff engineer - interconnect design
时间：12-12
整理：3721RD
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Job Overview
We are seeking interconnect design engineers to develop the next generation of Huaxintong's industry-leading custom ARM-compatible CPUs. Individuals in this team will be involved in all phases of product development, from proving-out initial high-level concepts down to modeling the bits of individual registers. We need engineers who can help us design and implement interconnect fabric. In this team, individuals will work with CPU performance modeling team and verification team to design the major blocks of the Huaxintong's next generation custom CPU. Use Hardware Description Language to design models of the coherence bus system. Employ synthesis, STA and power tools to achieve improve performance with reasonable overhead.
Minimum Qualifications
We are looking for individuals that have 5+ years’ experience or equivalent education in the following areas:
1. Good understanding of RISC and CPU architecture.
2. Achieve improve performance with reasonable microarchitecture.
3. Work with verification team and integration team
4. High performance logic design techniques Familiar withHDL and behavior modeling
5. Experience with simulation and design flow, such as lint, CDC, synthesis, STA, floorplan and etc.
Preferred Qualifications
Additional skills in the following areas are a plus:
1. Industry experience in a specific high performance CPU design.
2. Experience with coherence protocol implementation, such as ACE, CHI/CHIE.
3. Experience with cache system design.
4. Knowledge of verification and good communication skill with verification team
Education Requirements
Required: Master’s, Electronic Engineering and/or Computer Science
Preferred: Doctorate, Electronic Engineering and/or Computer Science or equivalent experience.
工作地点北京/上海
感兴趣的请私信我！
We are seeking interconnect design engineers to develop the next generation of Huaxintong's industry-leading custom ARM-compatible CPUs. Individuals in this team will be involved in all phases of product development, from proving-out initial high-level concepts down to modeling the bits of individual registers. We need engineers who can help us design and implement interconnect fabric. In this team, individuals will work with CPU performance modeling team and verification team to design the major blocks of the Huaxintong's next generation custom CPU. Use Hardware Description Language to design models of the coherence bus system. Employ synthesis, STA and power tools to achieve improve performance with reasonable overhead.
Minimum Qualifications
We are looking for individuals that have 5+ years’ experience or equivalent education in the following areas:
1. Good understanding of RISC and CPU architecture.
2. Achieve improve performance with reasonable microarchitecture.
3. Work with verification team and integration team
4. High performance logic design techniques Familiar withHDL and behavior modeling
5. Experience with simulation and design flow, such as lint, CDC, synthesis, STA, floorplan and etc.
Preferred Qualifications
Additional skills in the following areas are a plus:
1. Industry experience in a specific high performance CPU design.
2. Experience with coherence protocol implementation, such as ACE, CHI/CHIE.
3. Experience with cache system design.
4. Knowledge of verification and good communication skill with verification team
Education Requirements
Required: Master’s, Electronic Engineering and/or Computer Science
Preferred: Doctorate, Electronic Engineering and/or Computer Science or equivalent experience.
工作地点北京/上海
感兴趣的请私信我！
怎么投递申请
私信我或直接发简历到sibo.yang@hxt-semitech.com
5年就Sr staff了？
那你还不快投：）
继续~