CPU architecture validation Engineer
时间：12-12
整理：3721RD
点击：
华芯通半导体(http://www.hxt-semitech.com/)是贵州省和高通成立的国资控股的合资公司。 高通瞄准了ARMv8服务器市场，尤其是看中中国市场的发展潜力.中国zf要求芯片自主可控，所以未来国内的ARMv8服务器市场还是很有前景。希望有志人士积极投递简历，从事基于ARM体系结构的服务器芯片的研发工作。
薪酬：高于行业平均水平
工作地点：北京
公司文化：偏美企
本部门负责CPU core的研发。
为方便及时回复，欢迎感兴趣的同学投简历至550255434@163.com，邮件标题请注明：姓名+应聘职位+工作年限
JD：
Responsibilities for this position would involve but not be limited to:
maintain validation environment, verification/validation vectors, perform test
generate test report Identify issue and co-fix it with design engineer.
Develop/maintain flows and scripts tin support of validation ease-of-use and improvement of productivity.
Qualifications
1. Must have a Bachelors or Masters in Computer Science, Computer Engineering, Electrical Engineering or related fields
2. Minimum of 3 years of RTL design/verification experience at the master level
3. Minimum of 5 years of RTL design/verification experience at the bachelor level
4. Good English communication skills, both written and oral
5. Disciplined design approach, and ability to work smoothly with a team
6. Solid knowledge about verilog, System Verilog, c/c++
7. Knowledge of Computer Architecture
8. experience Python, Perl, and/or TCL for SW/HW co-simulation Additional
9. knowledge about ARM architecture is big plus point
PS.如果你对CPU感兴趣，如果你想了解软硬件如何协同工作，如果你想了解行业顶尖芯片设计公司的设计理念，如果你想学习ARM各方面详细知识，请联系我。因公司初期有很多培训学习的机会，感兴趣的同学请尽快投递简历，我们会在第一时间跟您联系。
薪酬：高于行业平均水平
工作地点：北京
公司文化：偏美企
本部门负责CPU core的研发。
为方便及时回复，欢迎感兴趣的同学投简历至550255434@163.com，邮件标题请注明：姓名+应聘职位+工作年限
JD：
Responsibilities for this position would involve but not be limited to:
maintain validation environment, verification/validation vectors, perform test
generate test report Identify issue and co-fix it with design engineer.
Develop/maintain flows and scripts tin support of validation ease-of-use and improvement of productivity.
Qualifications
1. Must have a Bachelors or Masters in Computer Science, Computer Engineering, Electrical Engineering or related fields
2. Minimum of 3 years of RTL design/verification experience at the master level
3. Minimum of 5 years of RTL design/verification experience at the bachelor level
4. Good English communication skills, both written and oral
5. Disciplined design approach, and ability to work smoothly with a team
6. Solid knowledge about verilog, System Verilog, c/c++
7. Knowledge of Computer Architecture
8. experience Python, Perl, and/or TCL for SW/HW co-simulation Additional
9. knowledge about ARM architecture is big plus point
PS.如果你对CPU感兴趣，如果你想了解软硬件如何协同工作，如果你想了解行业顶尖芯片设计公司的设计理念，如果你想学习ARM各方面详细知识，请联系我。因公司初期有很多培训学习的机会，感兴趣的同学请尽快投递简历，我们会在第一时间跟您联系。
自顶一下
帮顶
多谢多谢
@Xaoyao, 你俩是马甲吗
我是正版
哈哈，第一次看到那个id还真以为lee总
顶！d=====(￣▽￣*)b
+1
顶！d=====(￣▽￣*)b