北京华芯通少量验证职位Senior/Staff/Senior Staff

北京华芯通少量验证职位Senior/Staff/Senior Staff
简历请发邮箱 zheng.shen@hxt-semitech.com
Job Title: Senior IP verification engineer
Location:Beijing
Position Description
finish the verification tasks of the specific IPs which assigned by the IP DV team leader in time and in high quality
Responsibilities
Create the testplan and reviewed with the team leader and designer
Create the random constraint testbench based on the requirement
Create the random testcase and the direct testcase to cover the IP design feature
Debug the testbench and RTL, and report the bug to designer
Finish the verification tasks in time
Qualifications
Education and Experience
Bachelor or above with 3 years work experience
Skills and Knowledge
System Verilog
UVM
C++ is an additional plus
Formal verification experience is an additional plus
PCIE/SATA/USB/Ethernet/SPI/I2C/etc experience is an additional plus
Job Title: Staff IP verification engineer
Location:Beijing
Position Description
Lead or co-lead the IP verification team to finish one IP’s verification, take charge of the verification quality and the schedule
Responsibilities
Lead the IP verification, and decompose the tasks into each team member
Create the testplan and reviewed with the team member and designer; make sure the testplan is completed and with details and measured
Create the random constraint testbench based on the requirement; and make sure team members implement corectly
Create the random testcase and the direct testcase to cover the IP design feature, and all required featured was covered
Debug the testbench and RTL, and report the bug to designer; follow up the whole IP’s status
Finish the verification tasks in time
Qualifications
Education and Experience
Bachelor or above with 6~9 years work experience
Skills and Knowledge
System Verilog
UVM
C++ is an additional plus
Formal verification experience is an additional plus
PCIE/SATA/USB/Ethernet/SPI/I2C/etc experience is an additional plus
Job Title: Senior Staff IP verification engineer
Location:Beijing
Position Description
Lead the IP verification team to finish one or several IP’s verification, take charge of the verification quality and the schedule
Responsibilities
Lead the IP verification, and decompose the tasks into each team member
Create the testplan and reviewed with the team member and designer; make sure the testplan is completed and with details and measured
Create the random constraint testbench based on the requirement; and make sure team members implement correctly
Create the random testcase and the direct testcase to cover the IP design feature, and all required featured was covered
Debug the testbench and RTL, and report the bug to designer; follow up the whole IP’s status
Finish the verification tasks in time
Follow up the leading edge verification methodology, include but not limit to random constraint verification; formal verification, rule based verification, or portable stimulus
Qualifications
Education and Experience
Bachelor or above with 9~12+ years work experience
Skills and Knowledge
System Verilog
UVM
C++ is an additional plus
Formal verification experience is an additional plus
PCIE/SATA/USB/Ethernet/SPI/I2C/etc experience is an additional plus

又招？
听说现在薪酬给的没那么大方了？

估计预算超标了，而且也没一开始那么急了。