Re: Marvell(北京) ASIC Design/Verification Engineer

是

应聘

诚聘数字芯片设计验证工程师，工作地点在五道口。
Responsibility:
o    Work together with algorithm team and design team to develop testplan and testcase for various blocks in our Read Channel products.
o    Maintain and help improve our UVM based verification environment.
o    Guide junior verification engineers to improve our verification coverage and reduce number of tape out.
o    Research on some advanced verification technology such as assertion based formal verification.
Requirement:
o    Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 5+ years working experiences in ASIC design or verification.
o    Familiar with Verilog and RTL design
o    Familiar with System-Verilog and UVM verification methodology
o    Familiar with script languages(perl,tcl,sh etc.) is a plus
o    Familiar with digital signal processing knowledge is a plus
o    Good problem solving and communication skills
o    Good written and spoken English. Be able to work together with global team.
企业文化是纯美企风格，氛围好。
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Read Channel组是负责啥的？

硬盘用的芯片

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