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VCS仿真时不时error,清一下report,就好了,下次又error,请教

时间:12-12 整理:3721RD 点击:
VCS仿真时不时error,清一下report,就好了,下次又error,请教大家怎么办?
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UVM_INFO @ 2377130000: uvm_test_top.u_tb.u_vir_seqr [example_test_vseq] example_test_vseq post_body() dropping an uvm_test_done objection
UVM_INFO /eda/synopsys/VCS2014/etc/uvm/base/uvm_objection.svh(1268) @ 2377130000: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
Warning: Incorrect SIGSEGV signal handler override detected.
Signal handler at address 0x7f25b1ee27a0 seems to be overriding VCS signal handler
without setting SA_SIGINFO flag in the handler. Some VCS functionality will be lost.
Info: Most likely PLI or third party library seems to be overriding VCS SIGSEGV Signal Handler.
Please check PLI or third party library at address 0x7f25b1ee27a0 .
make: *** [run] Error 255

应该是verdi的问题,和vcs的版本不太兼容

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