模拟芯片版图设计工程师@北京中关村 创业园 简历发 hr@hi-talen
时间：12-12
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模拟芯片版图设计工程师@北京中关村 创业园 简历发 hr@hi-talent.com
岗位职责包括但不限制于：
1.与芯片设计工程师一起使用Cadence工具完成IC电路到版图的转换
2.模块级和顶层版图的设计和优化
3.完成DRC／LVS，保证版图的正确性，验证文件的修改和维护，完成jobview，确证生产的正确
4.能够理解和解决项目中出现的版图设计的问题
5.潜在的作为项目经理领导其他版图设计工程师
理想候选人的任职要求：
1.微电子或者电子工程专业本科或以上学历
2.具有不少于一年的模拟或者混合信号IC版图设计的经验
3.了解基本的电路和版图设计知识，例如器件的匹配，ESD和Latchup
4.关注细节，目标驱动，团队精神
5.良好的口头和书面沟通能力
6.较强的解决问题和项目管理能力
layout engineer@北京中关村 简历发 hr@Hi-talent.com
Responsibilities include but are not limited to:
1.Work with Design Engineer to layout production worthy IC in a variety of processes using Cadence design tools.
2.Analog block level and top level mask design and optimization
3.Run and interpret results from verification and extraction tools
4.Be capable of understanding and resolving issues between different desciples
5.Potential for managing other layout engineers as a project lead
The ideal candidates will have the following requirements:
1.BSEE or above degree in micro electronics or electrical engineering
2.1+ year of experience with analog or mixed signal layout design techniques.
3.Knowledge of fundamental layout and analog circuits, i.e device matching, ESD, latch up etc.
4.Goal driven contributor who pay attention to details and has the ability to work as part of team
5.Excellent verbal and written communication skills
6.Good problem solving and project management skills
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
website： www.hi-talent.cn
岗位职责包括但不限制于：
1.与芯片设计工程师一起使用Cadence工具完成IC电路到版图的转换
2.模块级和顶层版图的设计和优化
3.完成DRC／LVS，保证版图的正确性，验证文件的修改和维护，完成jobview，确证生产的正确
4.能够理解和解决项目中出现的版图设计的问题
5.潜在的作为项目经理领导其他版图设计工程师
理想候选人的任职要求：
1.微电子或者电子工程专业本科或以上学历
2.具有不少于一年的模拟或者混合信号IC版图设计的经验
3.了解基本的电路和版图设计知识，例如器件的匹配，ESD和Latchup
4.关注细节，目标驱动，团队精神
5.良好的口头和书面沟通能力
6.较强的解决问题和项目管理能力
layout engineer@北京中关村 简历发 hr@Hi-talent.com
Responsibilities include but are not limited to:
1.Work with Design Engineer to layout production worthy IC in a variety of processes using Cadence design tools.
2.Analog block level and top level mask design and optimization
3.Run and interpret results from verification and extraction tools
4.Be capable of understanding and resolving issues between different desciples
5.Potential for managing other layout engineers as a project lead
The ideal candidates will have the following requirements:
1.BSEE or above degree in micro electronics or electrical engineering
2.1+ year of experience with analog or mixed signal layout design techniques.
3.Knowledge of fundamental layout and analog circuits, i.e device matching, ESD, latch up etc.
4.Goal driven contributor who pay attention to details and has the ability to work as part of team
5.Excellent verbal and written communication skills
6.Good problem solving and project management skills
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
website： www.hi-talent.cn