（北京/上海）外资公司验证
时间：12-12
整理：3721RD
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Lead Verification Engineer (Location: SH)
Position Description:
· Deliver/implement advanced verification solutions by utilizing the Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.
· Specific duties include:
· Deep understanding on ASIC design and verification flow
· Excellent knowledge of advanced verification methodology likeeRM/OVM/UVM/VMM
· Familiar with the Incisive Plan to Closure Methodology (IPCM)
· Proficiency in System Verilog, System C and/or e (Specman)
· Developing and using Verification Components (eVC, OVC,UVC,VIP)
· Developing and using assertion based verification and formal analysis methods
· Skilled in scripting language, such as Perl, C shell, Python, Make file
· Assessing the project verification requirements
Position Requirements:
· MS degree with 3+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
· Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.
· Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.
· Will have demonstrated successful completion of 3+ verification projects as an individual contributor
· Will have DDR project verification experience
硕士3-5年，有DDR经验优先，250-400K/Y
感兴趣者可电话咨询18866916715Tony或咨询/简历1432148616@qq.com
Position Description:
· Deliver/implement advanced verification solutions by utilizing the Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.
· Specific duties include:
· Deep understanding on ASIC design and verification flow
· Excellent knowledge of advanced verification methodology likeeRM/OVM/UVM/VMM
· Familiar with the Incisive Plan to Closure Methodology (IPCM)
· Proficiency in System Verilog, System C and/or e (Specman)
· Developing and using Verification Components (eVC, OVC,UVC,VIP)
· Developing and using assertion based verification and formal analysis methods
· Skilled in scripting language, such as Perl, C shell, Python, Make file
· Assessing the project verification requirements
Position Requirements:
· MS degree with 3+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
· Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.
· Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.
· Will have demonstrated successful completion of 3+ verification projects as an individual contributor
· Will have DDR project verification experience
硕士3-5年，有DDR经验优先，250-400K/Y
感兴趣者可电话咨询18866916715Tony或咨询/简历1432148616@qq.com
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