北京职位来袭-数字前端 验证 DFT
时间：12-12
整理：3721RD
点击：
如题，目前客户在北京急需人，上班地点丰台与石景山区中间 有兴趣的可以投简历到hamy_wang@126.com 或者加QQ:1349541957
数字前端设计
最好是有AMD 经验的，五年左右的工作经验
soc 验证
JOB DESCRPTION:
- Build up the emulation platform including develop scripts to implement the compilation and working flow with Python
- Support to bring up the legal project on emulation platform including remodeling for PLL/PHY
- Integrate the Questa simulation tool-chain into current simulation flow and support the co-simulation among sim and emu platform
QUALIFICATION:
KEY KNOWLEDGE, SKILLS AND ABBILITIES REQUIRED
- On-hands experiences with emulation platform (Mentor’s Veloce or Cadence’s PXP), have the knowledge on the compilation and working flow
- Solid experience on Verilog/System Verilog design/modeling
- Solid experience on script development with Python
- Be familiar with the simulation compilation flow about IES or Questa or VCS
- Be familiar with the testbench setup and have DPI experience
senior DFT engineer
岗位描述
This position will be assigned to work oversea in countries such as Korea/Japan. Experience with Cadence DFT architect tool will be a plus.
Job Description:
1. Perform DFT design and verification tasks for SoC including SCAN insertion, MBIST, functional test logic etc..
2. support DFT related timing constraints and work with physical design team
3. Generate and verify DFT ATPG and functional patterns
4. Other tasks assigned by customer's manager
Requirements:
- BS in EE, MS preferred., with minimal 3 years working experience on DFT
- familiar with DFT tools like TestKompress, FastScan, Tetra max ,MBISTarchitect, BSDarchitect etc..
- Should have strong problem solving skills - Good English hearing, speaking, reading and writing capabilities
- Good team working spirit
数字前端设计
最好是有AMD 经验的，五年左右的工作经验
soc 验证
JOB DESCRPTION:
- Build up the emulation platform including develop scripts to implement the compilation and working flow with Python
- Support to bring up the legal project on emulation platform including remodeling for PLL/PHY
- Integrate the Questa simulation tool-chain into current simulation flow and support the co-simulation among sim and emu platform
QUALIFICATION:
KEY KNOWLEDGE, SKILLS AND ABBILITIES REQUIRED
- On-hands experiences with emulation platform (Mentor’s Veloce or Cadence’s PXP), have the knowledge on the compilation and working flow
- Solid experience on Verilog/System Verilog design/modeling
- Solid experience on script development with Python
- Be familiar with the simulation compilation flow about IES or Questa or VCS
- Be familiar with the testbench setup and have DPI experience
senior DFT engineer
岗位描述
This position will be assigned to work oversea in countries such as Korea/Japan. Experience with Cadence DFT architect tool will be a plus.
Job Description:
1. Perform DFT design and verification tasks for SoC including SCAN insertion, MBIST, functional test logic etc..
2. support DFT related timing constraints and work with physical design team
3. Generate and verify DFT ATPG and functional patterns
4. Other tasks assigned by customer's manager
Requirements:
- BS in EE, MS preferred., with minimal 3 years working experience on DFT
- familiar with DFT tools like TestKompress, FastScan, Tetra max ,MBISTarchitect, BSDarchitect etc..
- Should have strong problem solving skills - Good English hearing, speaking, reading and writing capabilities
- Good team working spirit
去韩国日本，技术外包么？