知名美资公司IP团队frontend design engineer（上海/北京）
时间：12-12
整理：3721RD
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Title: Lead Design Engineer (数字前端设计)
Location: SH/BJ
Position Description:
Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies.
Specific duties include:
1.Proficiency in logic design, simulation, synthesis, STA and testing
2.Proficiency in Verilog and its simulation environment
3.Good knowledge of IC design
4.At least two years’ experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.
Position Requirements:
1. Essential Qualifications: Must have BS degree with 4+ years of applicable experience, MS degree with 2+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written.
Requires good communication skills in English.
Desirable Qualifications:
1.Will have demonstrated successful completion of 5+ design projects as an individual contributor
2.Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience
硕士2-5年，前端设计（两个方向1、Coding ；2、Synthesis DFT Timing）
有DDR设计经验优先，英语口语好优先。感兴趣者可发简历1432148616@qq.com或者直接QQ咨询，电话18866916715Tony
Location: SH/BJ
Position Description:
Deliver/implement DDR/HBM IP. The engineer should be able to act as a strong team member and contributor. Exercise judgment within generally defined practices and policies.
Specific duties include:
1.Proficiency in logic design, simulation, synthesis, STA and testing
2.Proficiency in Verilog and its simulation environment
3.Good knowledge of IC design
4.At least two years’ experience driving complex IC development projects, excellent communication skills and the uncanny ability to both lead and contribute in a cooperative team environment.
Position Requirements:
1. Essential Qualifications: Must have BS degree with 4+ years of applicable experience, MS degree with 2+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics.
2. Essential that the individual demonstrates strong communication, verbal and written.
Requires good communication skills in English.
Desirable Qualifications:
1.Will have demonstrated successful completion of 5+ design projects as an individual contributor
2.Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols and have DDR project design experience
硕士2-5年，前端设计（两个方向1、Coding ；2、Synthesis DFT Timing）
有DDR设计经验优先，英语口语好优先。感兴趣者可发简历1432148616@qq.com或者直接QQ咨询，电话18866916715Tony
很match，多少钱
cadence?
eetop上面有原厂招聘贴
这个贴 那个贴 哪个命中概率更大?
update