marvell 美满电子 video 相关
时间：12-12
整理：3721RD
点击：
我们组是做video codec，有三个opening
1. RTL designer
有三年以上verilog经验，熟悉开发流程，有流片经验，懂一些后端加分，最好有video背
景
Digital IC Design Engineer
Location: Shanghai
Description:
o Participate in high performance multi-standard video decoder IP development.
o Responsible for new video standard study, micro-architecture design, RTL implementation, design verification in simulation and on FPGA emulation platforms.
o Interact with peer teams (modeling, verification, software etc.) and take ownership in some key areas/modules.
Qualification:
o BS with 6 years’ experience, or MS with 3 years’ experience, or PhD or equivalent.
o Excellent knowledge of RTL design and verification.
o Knowledge of video encoding/decoding algorithms and modern video standards such as HEVC/H.264/VP9.
o Hands-on experience with Verilog, C/C++, Perl, Tcl.
o Experience in video encoding/decoding firmware/driver is a plus.
2. DV
c 语言，systemverilog 经验，最好有video背景，熟悉起码一种video标准
Design Verification Engineer
Location: Shanghai
Description:
o A design verification engineer in Marvell's video system group working on high performance video codec development.
o Responsibilities will include C model development and validation, test planning, testbench creation, test generating, and software/hardware co-simulation and debug.
o This person will work closely with architecture and design team to ensure functional and performance targets are met.
Qualification:
o BS, MS, PHD in Computer Science or Electrical Engineering
o Strong programming skills in C/C++.
o Excellent knowledge of video standards such as H.265, H.264, VP9.
o Advanced verification methodology such as UVM or OVM experience is a plus.
3. firmware
c 语言，有嵌入式开发和fpga经验优先，video背景要求可以弱一些，有linux开发经验加
分，有multimedia framework 经验加分。
Firmware Design Engineer
Location: Shanghai
Justification: The video codec firmware team is responsible for firmware development and design verification for the new IPs and supporting multiple key customers (e.g. Google, LG) for the existing IPs in production.
Description:
o Develop firmware for Marvell’s next generation high performance multi-format video codec.
o Support internal and external customers and resolve functional and performance issues.
o Validate video codec IPs on FPGA platforms.
o Participate in architecture definition and design verification of hardware video codec IPs.
Qualification: o BS or MS in EE/CS with 2+ years’ experience
o Proficient in C/C++
o Familiar with modern video coding standards, such as HEVC, H.264, VP9, etc.
o Experience in embedded software development
o Some knowledge of hardware description language (e.g. Verilog) is a plus
感兴趣可以发送简历到
jasonh001@126.com
headcount已有，会尽快安排面试，地点上海张江
1. RTL designer
有三年以上verilog经验，熟悉开发流程，有流片经验，懂一些后端加分，最好有video背
景
Digital IC Design Engineer
Location: Shanghai
Description:
o Participate in high performance multi-standard video decoder IP development.
o Responsible for new video standard study, micro-architecture design, RTL implementation, design verification in simulation and on FPGA emulation platforms.
o Interact with peer teams (modeling, verification, software etc.) and take ownership in some key areas/modules.
Qualification:
o BS with 6 years’ experience, or MS with 3 years’ experience, or PhD or equivalent.
o Excellent knowledge of RTL design and verification.
o Knowledge of video encoding/decoding algorithms and modern video standards such as HEVC/H.264/VP9.
o Hands-on experience with Verilog, C/C++, Perl, Tcl.
o Experience in video encoding/decoding firmware/driver is a plus.
2. DV
c 语言，systemverilog 经验，最好有video背景，熟悉起码一种video标准
Design Verification Engineer
Location: Shanghai
Description:
o A design verification engineer in Marvell's video system group working on high performance video codec development.
o Responsibilities will include C model development and validation, test planning, testbench creation, test generating, and software/hardware co-simulation and debug.
o This person will work closely with architecture and design team to ensure functional and performance targets are met.
Qualification:
o BS, MS, PHD in Computer Science or Electrical Engineering
o Strong programming skills in C/C++.
o Excellent knowledge of video standards such as H.265, H.264, VP9.
o Advanced verification methodology such as UVM or OVM experience is a plus.
3. firmware
c 语言，有嵌入式开发和fpga经验优先，video背景要求可以弱一些，有linux开发经验加
分，有multimedia framework 经验加分。
Firmware Design Engineer
Location: Shanghai
Justification: The video codec firmware team is responsible for firmware development and design verification for the new IPs and supporting multiple key customers (e.g. Google, LG) for the existing IPs in production.
Description:
o Develop firmware for Marvell’s next generation high performance multi-format video codec.
o Support internal and external customers and resolve functional and performance issues.
o Validate video codec IPs on FPGA platforms.
o Participate in architecture definition and design verification of hardware video codec IPs.
Qualification: o BS or MS in EE/CS with 2+ years’ experience
o Proficient in C/C++
o Familiar with modern video coding standards, such as HEVC, H.264, VP9, etc.
o Experience in embedded software development
o Some knowledge of hardware description language (e.g. Verilog) is a plus
感兴趣可以发送简历到
jasonh001@126.com
headcount已有，会尽快安排面试，地点上海张江
传闻最近裁人概率不小, video这个组看来很安全嘛.
不是全面转向用hantro了嘛
怎么又自己做了？
怎么可能，一直自己做。芯原的IP更不会用了。
芯原的video team老大说他们的IP很厉害啊，性能压缩率都超级好，为啥不用了呢？
难道就因为新CEO不是亲戚了？
这个节骨眼还招人？
MRVL的手机芯片组没做成一部分原因就是被戴家老三的GPU坑了吧……
.197
早点还别家的还是有可能苟延残喘的
主要原因还是一代枭雄吧……
.197
gpu是表层原因，根本原因还是老板老板娘的管理能力不行。
都一样的标准了，最多做点码控压缩率能高到哪里去嘛，这牛吹的
不止是概率问题
那是啥，已成定局？
又裁？
肯定的
这个坑可以入吗?
理性思考可以得出结论。
没有北京职位呀