新加坡Marvell招人（9月30号截止）
时间：12-12
整理：3721RD
点击：
事出突然，所以尽管前边有过上海Marvell招人的帖子了，还是把新加坡那边招人的信
息发一下。请特别注意最后的说明：在9月30号前把简历、期望的薪水等信息发到
hr@marvell.com.sg
1) SENIOR ANALOG/RF DESIGN ENGINEER (Code: ADWLCH01)
The Job:
Design state-of-art analog/RF integrated circuit building blocks in
advanced CMOS process technologies
Develop advanced wireless system and high performance RF transceiver
circuits
Perform correlation and silicon evaluation in laboratory
Requirements:
PhD or a good Masters/Bachelor’s Degree in Electronics/Electrical
Engineering from a reputable university with 3 years’ experience.
Experience in IC Design in one of the areas such as PA, LNA, Mixer,
Gm-C filter, ADC, DAC and mixed-signal design
Experience with Cadence design tools (Analog Artist, SpectreRF,
Goldengate) is required
Knowledge of communication standards (GSM, EDGE, UMTS, LTE etc) and
mixed signal components
Familiar with RF test equipment including VSA, network analyzer etc.
Fresh Graduates with good academic record are also welcome to apply
2) SENIOR/ANALOG DESIGN ENGINEERS (Code: ADPACH01)
The Job:
Design ultra-wide bandwidth low noise analog amplifiers and high
performance high output swing drivers using the advanced SiGe BiCMOS process
Support data converters, generic amplifiers, comparators, precision
voltage and current references design
Perform detailed transistor-level design, simulation and high speed
bench verification
Requirements:
Good Masters/Bachelor’s Degree in Electronics/Electrical
Engineering with minimum 3 years’ relevant experience
A thorough understanding of CMOS/SiGe analog device and circuit
analysis
Experience in high frequency circuit design and layout requirements
Knowledge and experience in high speed bench measurement techniques
is a plus
3) SENIOR/ASIC VERIFICATION ENGINEER (Code: DDASCH01)
The Job:
Develop a state-of-the-art verification environment for networking
switch/routers and SoCs
Develop and implement a strategy for fast coverage closure using
intelligent testbench automation tools
Create and/or integrate Verification IP for protocols such as
Ethernet, USB, PCIE, SATA
Implement an advanced performance measurement infrastructure for
real-time, jitter-sensitive protocols
Improve the testbench and simulation wrapper scripts to accelerate
regression testing, especially for constrained-random tests
Requirements:
Good Bachelor’s / Master Degree in Electronics/Electrical
Engineering with coursework in digital logic design, computer architecture,
and networking preferred
Proficient in object oriented programming
Experience with a high-level verification language such as
SystemVerilog, Vera, or e, as well as advanced verification methodology such
as VMM, OVM, or eRM
Knowledge of Ethernet and/or SoC protocols such as DDR, AMBA, USB,
PCIE and SATA
Interested candidates, please e-mail the respective job code, your resume,
degree and transcripts with contact nos. and current & expected salaries to:
hr@marvell.com.sg
The Human Resource Department
MARVELL ASIA PTE LTD
(Regn No.: 199702379M)
8 Tai Seng Link
Singapore 534158
Closing Date: 30 September 2010
Only shortlisted candidates will be notified
息发一下。请特别注意最后的说明：在9月30号前把简历、期望的薪水等信息发到
hr@marvell.com.sg
1) SENIOR ANALOG/RF DESIGN ENGINEER (Code: ADWLCH01)
The Job:
Design state-of-art analog/RF integrated circuit building blocks in
advanced CMOS process technologies
Develop advanced wireless system and high performance RF transceiver
circuits
Perform correlation and silicon evaluation in laboratory
Requirements:
PhD or a good Masters/Bachelor’s Degree in Electronics/Electrical
Engineering from a reputable university with 3 years’ experience.
Experience in IC Design in one of the areas such as PA, LNA, Mixer,
Gm-C filter, ADC, DAC and mixed-signal design
Experience with Cadence design tools (Analog Artist, SpectreRF,
Goldengate) is required
Knowledge of communication standards (GSM, EDGE, UMTS, LTE etc) and
mixed signal components
Familiar with RF test equipment including VSA, network analyzer etc.
Fresh Graduates with good academic record are also welcome to apply
2) SENIOR/ANALOG DESIGN ENGINEERS (Code: ADPACH01)
The Job:
Design ultra-wide bandwidth low noise analog amplifiers and high
performance high output swing drivers using the advanced SiGe BiCMOS process
Support data converters, generic amplifiers, comparators, precision
voltage and current references design
Perform detailed transistor-level design, simulation and high speed
bench verification
Requirements:
Good Masters/Bachelor’s Degree in Electronics/Electrical
Engineering with minimum 3 years’ relevant experience
A thorough understanding of CMOS/SiGe analog device and circuit
analysis
Experience in high frequency circuit design and layout requirements
Knowledge and experience in high speed bench measurement techniques
is a plus
3) SENIOR/ASIC VERIFICATION ENGINEER (Code: DDASCH01)
The Job:
Develop a state-of-the-art verification environment for networking
switch/routers and SoCs
Develop and implement a strategy for fast coverage closure using
intelligent testbench automation tools
Create and/or integrate Verification IP for protocols such as
Ethernet, USB, PCIE, SATA
Implement an advanced performance measurement infrastructure for
real-time, jitter-sensitive protocols
Improve the testbench and simulation wrapper scripts to accelerate
regression testing, especially for constrained-random tests
Requirements:
Good Bachelor’s / Master Degree in Electronics/Electrical
Engineering with coursework in digital logic design, computer architecture,
and networking preferred
Proficient in object oriented programming
Experience with a high-level verification language such as
SystemVerilog, Vera, or e, as well as advanced verification methodology such
as VMM, OVM, or eRM
Knowledge of Ethernet and/or SoC protocols such as DDR, AMBA, USB,
PCIE and SATA
Interested candidates, please e-mail the respective job code, your resume,
degree and transcripts with contact nos. and current & expected salaries to:
hr@marvell.com.sg
The Human Resource Department
MARVELL ASIA PTE LTD
(Regn No.: 199702379M)
8 Tai Seng Link
Singapore 534158
Closing Date: 30 September 2010
Only shortlisted candidates will be notified