关于virtual interface

需要set get把input_if 和vif连起来；
如果我在driver中名字和top保持一致  都改成input_if;
不使用set get，报错  # ** Fatal: (SIGSEGV) Bad handle or reference.
为什么 编译不认为这两个是一个，而必须使用set get将两者关联起来呢
interface my_if(input clk, input rst_n);
   logic [7:0] data;
   logic valid;
endinterface
top.sv
....
initial begin
   uvm_config_db#(virtual my_if)::set(null, "uvm_test_top", "vif", input_if);
end
class my_driver extends uvm_driver;
   //virtual my_if vif;
virtual my_if input_if;
   `uvm_component_utils(my_driver)
   function new(string name = "my_driver", uvm_component parent = null);
      super.new(name, parent);
      `uvm_info("my_driver", "new is called", UVM_LOW);
   endfunction
   virtual function void build_phase(uvm_phase phase);
      super.build_phase(phase);
      `uvm_info("my_driver", "build_phase is called", UVM_LOW);
     // if(!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif))
      //   `uvm_fatal("my_driver", "virtual interface must be set for vif!!!")
   endfunction
   extern virtual task main_phase(uvm_phase phase);
endclass
task my_driver::main_phase(uvm_phase phase);
   phase.raise_objection(this);
   `uvm_info("my_driver", "main_phase is called", UVM_LOW);
   input_if.data <= 8'b0;
   input_if.valid <= 1'b0;
   while(!input_if.rst_n)
      @(posedge input_if.clk);
   for(int i = 0; i < 256; i++)begin
      @(posedge input_if.clk);
      input_if.data <= $urandom_range(0, 255);
      input_if.valid <= 1'b1;
      `uvm_info("my_driver", "data is drived", UVM_LOW);
   end
   @(posedge input_if.clk);
   input_if.valid <= 1'b0;
   phase.drop_objection(this);
endtask
`endif

我觉得你看到bad handle的原因是你的interface没有new/creat过就被de-reference了
。
set get不是必须的，只要你有办法找到那个interface的reference。
set get的意义在于给你一个集中的resource pool，方便各个验证模块之间的解耦，也
方便DUT和test bench解耦
低端一点想，这个resource pool里面的东西就相当于全局变量。这样做各个验证模块的
时候就不用把一堆公用模块的索引当参数传进来了，只要每个模块自己知道想要什么东
西，从全局变量库里找就好了。
高端一点想，有助于优化验证环境的层次化。这个培训的老师讲过，当时明白了，不过
现在忘了。
.18

lass my_driver extends uvm_driver;
  
    //virtual my_if vif;
virtual my_if input_if;
  
    `uvm_component_utils(my_driver)
    function new(string name = "my_driver", uvm_component parent = null);
       super.new(name, parent);
       `uvm_info("my_driver", "new is called", UVM_LOW);
    endfunction
  
    virtual function void build_phase(uvm_phase phase);
       super.build_phase(phase);
       input_if = my_if::type_id::create("input_if", this);  //++++++++++++++++
//但是报错，是不是只有class才可以这样create呢  ，interface不行
       `uvm_info("my_driver", "build_phase is called", UVM_LOW);
      // if(!uvm_config_db#(virtual my_if)::get(this, "", "vif", vif))
       //   `uvm_fatal("my_driver", "virtual interface must be set for vif!!!")
    endfunction
  
    extern virtual task main_phase(uvm_phase phase);
endclass
  
task my_driver::main_phase(uvm_phase phase);
    phase.raise_objection(this);
    `uvm_info("my_driver", "main_phase is called", UVM_LOW);
    input_if.data <= 8'b0;  
    input_if.valid <= 1'b0;
    while(!input_if.rst_n)
       @(posedge input_if.clk);
    for(int i = 0; i < 256; i++)begin
       @(posedge input_if.clk);
       input_if.data <= $urandom_range(0, 255);
       input_if.valid <= 1'b1;
       `uvm_info("my_driver", "data is drived", UVM_LOW);
    end
    @(posedge input_if.clk);
    input_if.valid <= 1'b0;
    phase.drop_objection(this);
endtask
`endif