验证小白问个多文件编译的问题
时间:12-12
整理:3721RD
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编译器说d.sv找不到data这个类型 怎么解决呢
写一个文件a.sv
class data extends uvm_sequence_item;
rand bit[7:0] d;
`uvm_object_utils_begin(data)
`uvm_field_int(d, UVM_DEFAULT)
`uvm_object_utils_end
function new(string name= "data");
super.new(name);
endfunction
endclass
//d.sv
class driver_1 extends uvm_driver#(data);
`uvm_component_utils(driver_1)
virtual d_if vif;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
void’(uvm_config_db#(virtual d_if)::get(this, "", "vif", vif));
endfunction
task main_phase(uvm_phase phase);
vif.en <= 1’b0;
vif.data <= 8’b0;
while(!vif.rst_n)
@(posedge vif.clk);
while(1) begin
seq_item_port.get_next_item(req);
repeat(2) @(posedge vif.clk);
vif.en <= 1’b1;
vif.data <= req.d;
$display("data = %h",vif.data);
@(posedge vif.clk);
vif.en <= 1’b0;
seq_item_port.item_done();
end
endtask
endclass
写一个文件a.sv
class data extends uvm_sequence_item;
rand bit[7:0] d;
`uvm_object_utils_begin(data)
`uvm_field_int(d, UVM_DEFAULT)
`uvm_object_utils_end
function new(string name= "data");
super.new(name);
endfunction
endclass
//d.sv
class driver_1 extends uvm_driver#(data);
`uvm_component_utils(driver_1)
virtual d_if vif;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
void’(uvm_config_db#(virtual d_if)::get(this, "", "vif", vif));
endfunction
task main_phase(uvm_phase phase);
vif.en <= 1’b0;
vif.data <= 8’b0;
while(!vif.rst_n)
@(posedge vif.clk);
while(1) begin
seq_item_port.get_next_item(req);
repeat(2) @(posedge vif.clk);
vif.en <= 1’b1;
vif.data <= req.d;
$display("data = %h",vif.data);
@(posedge vif.clk);
vif.en <= 1’b0;
seq_item_port.item_done();
end
endtask
endclass
没报req.d找不到?
都报了
我举一个例子就够了
文件列表中把a.sv放在d.sv前面。
或者d.sv开头加typedef class data;