Cadence上海招数字后端design service AE
时间：12-12
整理：3721RD
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工作地点：上海浦东
这个职位在AE部门，但主要是做design service，偏向研发方向
投递邮箱：cecilyl@cadence.com
Position Description:
1) The candidates should be senior in a way that they are not only technical excellent but also mature & able to talk to customers, advise customers as well as other, following team members. This engineer should have excellent design experiences in the digital implementation domain including Floorplan, P&R, STA, Physical verification, DFM.
2) The engineer must have a solid background in circuits, electronics & physics & should be very willing to learn new stuff.
3) Key Accountabilities: Ability to handle large sized design implementation tasks & architectural tasks alone. Ability to assess Customer's Design environment, to understand his application needs & to build new Design environment based on specifications & available Cadence tool technology.
4) Ability to acquire a basic understanding of the (services) business environment of Cadence. Feeling responsible for technical delivery as well as business development & opportunity creation.
5) Behavioral competencies: Teamwork; Customer focus; Accountability; Communication; Leadership; Proactive;
Position Requirements:
Essential Qualifications:
1) MS degree with 7+/5+ years of applicable experience in electrical engineering, microelectronics.
2) Essential that the individual demonstrates strong communication, verbal and written, and reporting skills.
3) Good verbal and written communication skill in English is needed.
Desirable Qualifications:
1) Will have demonstrated hands-on experience and expertise with Cadence logical and physical design tools ( SoC Encounter, Conformal, QRC, Vstorm, ETS, PVS) or equivalent tools, flows and methodologies required to execute a physical design project.
2) Will have demonstrated successful completion of chip tapeout (40nm/and below tapeout and/or hierarchical implementation experience are a real plus) as an individual contributor
3) Is able to work on-site at customer premises, travel up to 30%, and put in long hours when required to meet customer deadline.
4) Experience in sign-off tools for STA, IR drop, power analysis, SI analysis is a plus
5) ARM core implementation experience is definitively a plus.
这个职位在AE部门，但主要是做design service，偏向研发方向
投递邮箱：cecilyl@cadence.com
Position Description:
1) The candidates should be senior in a way that they are not only technical excellent but also mature & able to talk to customers, advise customers as well as other, following team members. This engineer should have excellent design experiences in the digital implementation domain including Floorplan, P&R, STA, Physical verification, DFM.
2) The engineer must have a solid background in circuits, electronics & physics & should be very willing to learn new stuff.
3) Key Accountabilities: Ability to handle large sized design implementation tasks & architectural tasks alone. Ability to assess Customer's Design environment, to understand his application needs & to build new Design environment based on specifications & available Cadence tool technology.
4) Ability to acquire a basic understanding of the (services) business environment of Cadence. Feeling responsible for technical delivery as well as business development & opportunity creation.
5) Behavioral competencies: Teamwork; Customer focus; Accountability; Communication; Leadership; Proactive;
Position Requirements:
Essential Qualifications:
1) MS degree with 7+/5+ years of applicable experience in electrical engineering, microelectronics.
2) Essential that the individual demonstrates strong communication, verbal and written, and reporting skills.
3) Good verbal and written communication skill in English is needed.
Desirable Qualifications:
1) Will have demonstrated hands-on experience and expertise with Cadence logical and physical design tools ( SoC Encounter, Conformal, QRC, Vstorm, ETS, PVS) or equivalent tools, flows and methodologies required to execute a physical design project.
2) Will have demonstrated successful completion of chip tapeout (40nm/and below tapeout and/or hierarchical implementation experience are a real plus) as an individual contributor
3) Is able to work on-site at customer premises, travel up to 30%, and put in long hours when required to meet customer deadline.
4) Experience in sign-off tools for STA, IR drop, power analysis, SI analysis is a plus
5) ARM core implementation experience is definitively a plus.