Analog/Layout/Memory/Logic
时间：12-12
整理：3721RD
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Hi, now there are some job opportunities for both campus and experienced
engineers from Globalfoundries. Please see the following introduction of
Globalfoundries and job descriptions.
GLOBALFOUNDRIES has successfully completed the acquisition of IBM's
microelectronics business on July 1, 2015. In China, the former IBM China Chip
Design Center is now officially a part of GLOBALFOUNDRIES. It is a major step
towards securing industry leadership. First, the acquisition reflects our
company’s long-term commitment to investing in R&D for technology leadership.
We have strengthened our team with some of the brightest and most innovative
people in the industry. We have substantially increased our intellectual
property making GLOBALFOUNDRIES the holder of one of the largest semiconductor
patent portfolios in the world. Moreover, we have expanded our product
portfolio with technology differentiation for RF and wired/wireless
communications solutions and technology leadership in Front-End Modules for
mobile applications and ASICs for wired communications on advanced technology
nodes.
Job Title and Contact
o Logic Verification Engineer -- qian.hu@globalfoundries.com
o Memory Design Engineer -- xiaoli.hu@globalfoundries.com
o Analog Design Engineer -- wanxin.shao@globalfoundries.com
o Layout Design Engineer -- wanxin.shao@globalfoundries.com
Logic Verification Engineer
Location: Shanghai, Beijing
Responsibilities:
GLOBALFOUNDRIES Logic Verification Engineer is working on cutting-edge Digital
and Mixed-signal IP development for GLOBALFOUNDRIES worldwide clients,
including High Speed Serial Links, Protocols, Memory Interface, etc. By
employing the industry leading tools, state of the art methodology, and
innovative semiconductor leading technologies ranging from 32nm to 14nm and
beyond, you will be participating in the front-end logic verification or mixed
signal verification.
Requirements:
1. ME/EE/CS or background in related areas.
2. Research and/or development experience in one or more of the following
areas:
o Logic verification on the basis of the target system specification
o Mixed-signal model verification on advanced technologies
o Proficiency in programming and/or scripting languages is a plus
o Knowledge on Protocols, High Speed Serdes or DDR is a plus
3. Experience in one or more of the following application domains, is a plus
o High performance computing system, processor, chipset and ASICs
o High end communication, networking, mobile and data center applications
o Digital signal processing, sensor and Internet of Things
o Other emerging IT technology and industry areas
4. Good English skills, communication skills, and willingness to work with a
global team. Skill in other languages is a plus.
5. Good learning competency, self-motivated, and ability to work in diverse
areas in a flexible and dynamic environment.
Memory Design Engineer
Location: Shanghai, Beijing
Responsibilities:
GLOBALFOUNDRIES Memory Design Engineer is working on cutting-edge embedded
Memory IP development for GLOBALFOUNDRIES worldwide clients, including SRAM, R
A, RF, TCAM, ROM, etc. By employing the industry leading tools, state of the
art methodology, and innovative semiconductor leading technologies ranging
from 32nm to 14nm and beyond, you will be participating in:
o Design full custom circuits in the embedded memory arrays
o Simulate, verify and analyze memory functionality, performance and
statistical margin
o Perform functional verification, characterization and model-to-hardware
correlation
o Evaluate and optimize memory architecture and methodology in cutting-edge
technology
Requirements:
1. ME/EE or background in related areas.
2. Experience in one or more of the following embedded or standalone memory
products/circuits: SRAM, DRAM, Flash, RA, RF, TCAM, ROM, etc.
3. Familiar with transistor level circuit EDA tools (Virtuoso, Spectre, HSPICE
, etc.).
4. Good understanding of advanced semiconductor technology process and device
physics.
5. Experience with statistical circuit analysis and simulation is a plus.
6. Good English skills, communication skills, and willingness to work with a
global team. Skill in other languages is a plus.
7. Good learning competency, self-motivated, and ability to work in diverse
areas in a flexible and dynamic environment.
Analog Design Engineer
Location: Shanghai, Beijing
Responsibilities:
GLOBALFOUNDRIES Analog Design Engineer is working on cutting-edge Analog and
Mixed-signal IP development for GLOBALFOUNDRIES worldwide clients, including
High Speed Serial Links, PLL, ADC/DAC, etc. By employing the industry leading
tools, state of the art methodology, and innovative semiconductor leading
technologies ranging from 32nm to 14nm and beyond, you will be participating
in the definition, design, layout, and characterization of the analog and
mixed-signal circuits.
Requirements:
1. ME/EE or background in related areas.
2. Able to design circuits that operate effectively within the process window,
and supervise layout floorplan and design.
3. Demonstrate good knowledge and experience in advanced analog and mixed-
signal circuit design, experience in one or more of the following circuits, is
a plus:
o Driver / Receiver
o Serializer / Deserializer
o Phase Interpolator
o VCO, Charge Pump, Clock Divider, PFD
o Bias, Bandgap, Voltage Regulators
4. Familiar with transistor level circuit EDA tools (Virtuoso, Spectre, HSPICE
, etc.).
5. Good understanding of advanced semiconductor technology process and device
physics.
6. Experience with system level modeling and simulation by MATLAB, Verilog-A
or C/C++ is a plus.
7. Good English skills, communication skills, and willingness to work with a
global team. Skill in other languages is a plus.
8. Good learning competency, self-motivated, and ability to work in diverse
areas in a flexible and dynamic environment.
Layout Design Engineer
Location: Shanghai/Beijing
Responsibilities:
GLOBALFOUNDRIES is looking for a strong technical leader and design engineers
to join our world-class Layout team! Circuit Layout Engineers at GLOBALFOUNDRI
ES are responsible for creating circuit layouts (analog custom logic, mixed
signal) for our industry-leading SerDes offering. The ideal candidate will
have extensive experience with the layout of analog and some high speed custom
digital circuits for High Speed Serial IO Interfaces in ASIC applications.
Applicants must have several years of experience in this area must have
experience using the design tools associated with these tasks, preferably
Cadence tools, and must be familiar with current CMOS technology generations (
32nm and below). The layout engineer will direct the floor planning, lead
other layout designers with leaf cell and block creation, and integration of
analog blocks within the IP block. The person should be familiar with
learning new tools, methodologies, and technology. Applicants must be good
team players. Knowledge and/or experience with Serial Link applications is a
significant plus. Graduate level education with an emphasis in analog circuit
design is preferred.
Requirements:
1. BS in Electrical or Computer Engineering.
2. At least 2 years full-custom analog layout/verification and RC extraction
experience.
3. Experiences in Mixed signal/analog/high speed layout，SerDes、AD-DA、PLL，
etc.
4. Deep Experience with layout in the Cadence Design Environment. Familiar
with Virtuoso XL and physical verification tools (DRC,LVS,DFM,YCD,etc).
5. Experienced with Electro migration and voltage drop analysis.
6. Ability to recognize critical signal nets and reduce parasitics by proper
floorplanning/placement
7. Good understanding of advanced semiconductor technology process and device
physics.
8. Familiar with ESD/Latch up/antenna and related layout solutions is a plus.
9. Good English skills, communication skills, and willingness to work with a
global team.
10. Good learning competency, self-motivated, and ability to work in diverse
areas in a flexible and dynamic environment.
If you’re interested in any of the position above, you're welcome to contact
with us:) Look forward to getting your CV and working together with you in
future.
engineers from Globalfoundries. Please see the following introduction of
Globalfoundries and job descriptions.
GLOBALFOUNDRIES has successfully completed the acquisition of IBM's
microelectronics business on July 1, 2015. In China, the former IBM China Chip
Design Center is now officially a part of GLOBALFOUNDRIES. It is a major step
towards securing industry leadership. First, the acquisition reflects our
company’s long-term commitment to investing in R&D for technology leadership.
We have strengthened our team with some of the brightest and most innovative
people in the industry. We have substantially increased our intellectual
property making GLOBALFOUNDRIES the holder of one of the largest semiconductor
patent portfolios in the world. Moreover, we have expanded our product
portfolio with technology differentiation for RF and wired/wireless
communications solutions and technology leadership in Front-End Modules for
mobile applications and ASICs for wired communications on advanced technology
nodes.
Job Title and Contact
o Logic Verification Engineer -- qian.hu@globalfoundries.com
o Memory Design Engineer -- xiaoli.hu@globalfoundries.com
o Analog Design Engineer -- wanxin.shao@globalfoundries.com
o Layout Design Engineer -- wanxin.shao@globalfoundries.com
Logic Verification Engineer
Location: Shanghai, Beijing
Responsibilities:
GLOBALFOUNDRIES Logic Verification Engineer is working on cutting-edge Digital
and Mixed-signal IP development for GLOBALFOUNDRIES worldwide clients,
including High Speed Serial Links, Protocols, Memory Interface, etc. By
employing the industry leading tools, state of the art methodology, and
innovative semiconductor leading technologies ranging from 32nm to 14nm and
beyond, you will be participating in the front-end logic verification or mixed
signal verification.
Requirements:
1. ME/EE/CS or background in related areas.
2. Research and/or development experience in one or more of the following
areas:
o Logic verification on the basis of the target system specification
o Mixed-signal model verification on advanced technologies
o Proficiency in programming and/or scripting languages is a plus
o Knowledge on Protocols, High Speed Serdes or DDR is a plus
3. Experience in one or more of the following application domains, is a plus
o High performance computing system, processor, chipset and ASICs
o High end communication, networking, mobile and data center applications
o Digital signal processing, sensor and Internet of Things
o Other emerging IT technology and industry areas
4. Good English skills, communication skills, and willingness to work with a
global team. Skill in other languages is a plus.
5. Good learning competency, self-motivated, and ability to work in diverse
areas in a flexible and dynamic environment.
Memory Design Engineer
Location: Shanghai, Beijing
Responsibilities:
GLOBALFOUNDRIES Memory Design Engineer is working on cutting-edge embedded
Memory IP development for GLOBALFOUNDRIES worldwide clients, including SRAM, R
A, RF, TCAM, ROM, etc. By employing the industry leading tools, state of the
art methodology, and innovative semiconductor leading technologies ranging
from 32nm to 14nm and beyond, you will be participating in:
o Design full custom circuits in the embedded memory arrays
o Simulate, verify and analyze memory functionality, performance and
statistical margin
o Perform functional verification, characterization and model-to-hardware
correlation
o Evaluate and optimize memory architecture and methodology in cutting-edge
technology
Requirements:
1. ME/EE or background in related areas.
2. Experience in one or more of the following embedded or standalone memory
products/circuits: SRAM, DRAM, Flash, RA, RF, TCAM, ROM, etc.
3. Familiar with transistor level circuit EDA tools (Virtuoso, Spectre, HSPICE
, etc.).
4. Good understanding of advanced semiconductor technology process and device
physics.
5. Experience with statistical circuit analysis and simulation is a plus.
6. Good English skills, communication skills, and willingness to work with a
global team. Skill in other languages is a plus.
7. Good learning competency, self-motivated, and ability to work in diverse
areas in a flexible and dynamic environment.
Analog Design Engineer
Location: Shanghai, Beijing
Responsibilities:
GLOBALFOUNDRIES Analog Design Engineer is working on cutting-edge Analog and
Mixed-signal IP development for GLOBALFOUNDRIES worldwide clients, including
High Speed Serial Links, PLL, ADC/DAC, etc. By employing the industry leading
tools, state of the art methodology, and innovative semiconductor leading
technologies ranging from 32nm to 14nm and beyond, you will be participating
in the definition, design, layout, and characterization of the analog and
mixed-signal circuits.
Requirements:
1. ME/EE or background in related areas.
2. Able to design circuits that operate effectively within the process window,
and supervise layout floorplan and design.
3. Demonstrate good knowledge and experience in advanced analog and mixed-
signal circuit design, experience in one or more of the following circuits, is
a plus:
o Driver / Receiver
o Serializer / Deserializer
o Phase Interpolator
o VCO, Charge Pump, Clock Divider, PFD
o Bias, Bandgap, Voltage Regulators
4. Familiar with transistor level circuit EDA tools (Virtuoso, Spectre, HSPICE
, etc.).
5. Good understanding of advanced semiconductor technology process and device
physics.
6. Experience with system level modeling and simulation by MATLAB, Verilog-A
or C/C++ is a plus.
7. Good English skills, communication skills, and willingness to work with a
global team. Skill in other languages is a plus.
8. Good learning competency, self-motivated, and ability to work in diverse
areas in a flexible and dynamic environment.
Layout Design Engineer
Location: Shanghai/Beijing
Responsibilities:
GLOBALFOUNDRIES is looking for a strong technical leader and design engineers
to join our world-class Layout team! Circuit Layout Engineers at GLOBALFOUNDRI
ES are responsible for creating circuit layouts (analog custom logic, mixed
signal) for our industry-leading SerDes offering. The ideal candidate will
have extensive experience with the layout of analog and some high speed custom
digital circuits for High Speed Serial IO Interfaces in ASIC applications.
Applicants must have several years of experience in this area must have
experience using the design tools associated with these tasks, preferably
Cadence tools, and must be familiar with current CMOS technology generations (
32nm and below). The layout engineer will direct the floor planning, lead
other layout designers with leaf cell and block creation, and integration of
analog blocks within the IP block. The person should be familiar with
learning new tools, methodologies, and technology. Applicants must be good
team players. Knowledge and/or experience with Serial Link applications is a
significant plus. Graduate level education with an emphasis in analog circuit
design is preferred.
Requirements:
1. BS in Electrical or Computer Engineering.
2. At least 2 years full-custom analog layout/verification and RC extraction
experience.
3. Experiences in Mixed signal/analog/high speed layout，SerDes、AD-DA、PLL，
etc.
4. Deep Experience with layout in the Cadence Design Environment. Familiar
with Virtuoso XL and physical verification tools (DRC,LVS,DFM,YCD,etc).
5. Experienced with Electro migration and voltage drop analysis.
6. Ability to recognize critical signal nets and reduce parasitics by proper
floorplanning/placement
7. Good understanding of advanced semiconductor technology process and device
physics.
8. Familiar with ESD/Latch up/antenna and related layout solutions is a plus.
9. Good English skills, communication skills, and willingness to work with a
global team.
10. Good learning competency, self-motivated, and ability to work in diverse
areas in a flexible and dynamic environment.
If you’re interested in any of the position above, you're welcome to contact
with us:) Look forward to getting your CV and working together with you in
future.