职位名称：IC验证工程师 Design Verification engineer 简历发
时间：12-12
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职位名称：IC验证工程师 Design Verification engineer 简历发 offer@hi-talent.net
职位描述：
1.负责整个团队验证平台的搭建、维护
2.先进验证方法和验证平台的评估、导入
3.各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
岗位要求：
1.大学本科及以上学历，电子、通信、计算机或微电子专业
2.5-6年芯片验证的相关工作经验
3.熟悉verilog、System verilog、C/C++，有扎实的数字电路基础
4.熟悉SOC验证开发流程，了解常用的验证方法学，如VMM等
5.熟悉linux/unix环境，掌握per/python和unix shell语言
Job Description：
1.Take charge of verification platform development, and maintenance the plaform.
2.Familiar with verification methodologies and developing the platform.
3.Knowledge about IP block verfication, SOC integrated verification,system verification.Take charge of planning and pushing the team work of verification.Enable to write the Test Bench.
Requirements:
1.Majors in Electronics,Telecommunication,Computer or Micro Electronics.Bachelor or above degree.
2.At least 1 year Design Verification experience.
3.Familiar with verilog,System verilog,C/C++,rich knowledge about the digital circuit.
4.Familiar with SOC design verfication flow.Know about the verification methodologies,such as VMM etc.
5.Familiar with Linux/Unix,know about perl,python and unix shell.
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
webside： www.hi-talent.cn
职位描述：
1.负责整个团队验证平台的搭建、维护
2.先进验证方法和验证平台的评估、导入
3.各种IP的模块验证，SOC相关的集成验证、系统验证，负责验证计划的制定实施、测试用例的编写。
岗位要求：
1.大学本科及以上学历，电子、通信、计算机或微电子专业
2.5-6年芯片验证的相关工作经验
3.熟悉verilog、System verilog、C/C++，有扎实的数字电路基础
4.熟悉SOC验证开发流程，了解常用的验证方法学，如VMM等
5.熟悉linux/unix环境，掌握per/python和unix shell语言
Job Description：
1.Take charge of verification platform development, and maintenance the plaform.
2.Familiar with verification methodologies and developing the platform.
3.Knowledge about IP block verfication, SOC integrated verification,system verification.Take charge of planning and pushing the team work of verification.Enable to write the Test Bench.
Requirements:
1.Majors in Electronics,Telecommunication,Computer or Micro Electronics.Bachelor or above degree.
2.At least 1 year Design Verification experience.
3.Familiar with verilog,System verilog,C/C++,rich knowledge about the digital circuit.
4.Familiar with SOC design verfication flow.Know about the verification methodologies,such as VMM etc.
5.Familiar with Linux/Unix,know about perl,python and unix shell.
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
微信： xinde_jane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
webside： www.hi-talent.cn
BJ or SH?