DFT 上海
时间：12-12
整理：3721RD
点击：
DFT （赶紧 半个月内到位，简历发Jane-Jin@hi-talent.com）
职位职能: 集成电路IC设计/应用工程师
职位描述:
JOB RESPONSIBILITIES
The candidate is expected to be responsible for following tasks:
- Participate in SOC full Chip DFT feature and architecture definition
- Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
- Generate DFT related timing constraints and work for timing closure
- Develop and verify high coverage and cost effective test patterns for the production test
- Evaluate and establish the advanced DFT tools and flow
EDUCATION REQUIREMENTS
Bachelor degree in Electrical Engineering or related area, MSEE is preferred
YEARS OF EXPERIENCE REQUIREMENT
8+ years of experience in DFT design and verification, test pattern development
KEY KNOWLEDGE, SKILLS AND ABBILITIES REQUIRED
- Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques
- Good Knowledge of industry DFT tools like TestKompress, FastScan, Tetra max ,Tessent Mbist etc
- Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding
- Proficient in hardware description languages such as Verilog, System Verilog and VHDL
- Good Knowledge of script language, such as Tcl, Python, Perl
- Good English communication skills
- Strong commitment to schedule and work quality, good team player
Best Regards
Jane Jin
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯相会企业管理咨询有限公司
上海芯得企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
QQ: 157575516
Blog: http://blog.sina.com.cn/u/1716864892
Weibo: http://weibo.com/u/1716864892
webside： www.hi-talent.cn
职位职能: 集成电路IC设计/应用工程师
职位描述:
JOB RESPONSIBILITIES
The candidate is expected to be responsible for following tasks:
- Participate in SOC full Chip DFT feature and architecture definition
- Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic
- Generate DFT related timing constraints and work for timing closure
- Develop and verify high coverage and cost effective test patterns for the production test
- Evaluate and establish the advanced DFT tools and flow
EDUCATION REQUIREMENTS
Bachelor degree in Electrical Engineering or related area, MSEE is preferred
YEARS OF EXPERIENCE REQUIREMENT
8+ years of experience in DFT design and verification, test pattern development
KEY KNOWLEDGE, SKILLS AND ABBILITIES REQUIRED
- Good Knowledge of Scan/ATPG, MBIST and boundary scan and other DFT techniques
- Good Knowledge of industry DFT tools like TestKompress, FastScan, Tetra max ,Tessent Mbist etc
- Good knowledge of digital SoC/ASIC design, including STA, verification and RTL coding
- Proficient in hardware description languages such as Verilog, System Verilog and VHDL
- Good Knowledge of script language, such as Tcl, Python, Perl
- Good English communication skills
- Strong commitment to schedule and work quality, good team player
Best Regards
Jane Jin
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯相会企业管理咨询有限公司
上海芯得企业管理咨询有限公司
Mob: 18502155252
E-Mail: Jane-Jin@hi-talent.com
QQ: 157575516
Blog: http://blog.sina.com.cn/u/1716864892
Weibo: http://weibo.com/u/1716864892
webside： www.hi-talent.cn