求两篇paper，谢谢了。
时间：12-12
整理：3721RD
点击：
1. Ahmed M, Christopher D, Robert S, et al. A 14-bit 125 MS/s
IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter. IEEE J Solid-
State Circuits, 2006, 41: 1846
2. Chang D Y. Design techniques for a pipelined ADC without using
a front-end sample-and-hold amplifier. IEEE Trans Circuits Syst,
2004, 51(11): 2123
谢谢了。
IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter. IEEE J Solid-
State Circuits, 2006, 41: 1846
2. Chang D Y. Design techniques for a pipelined ADC without using
a front-end sample-and-hold amplifier. IEEE Trans Circuits Syst,
2004, 51(11): 2123
谢谢了。
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