上海InvenSense热招持续进行中,数字设计/验证
时间：12-12
整理：3721RD
点击：
这周已经陆续对之前投简历的候选者进行了面试，热招持续进行中, 请有兴趣者踊跃投递简历。
重点：这是InvenSense在上海成立R&D 之后的第一轮社招，刚开始扩张，机会应该是相当不错的。
1.Digital RTL Design and Implementation (synthesis \ DFT \ Timing Closure) Engineer
Location: Shanghai
Responsibilities:
• Digital RTL design and implementation for mixed signal/SoC ICs
• Starting from Verilog RTL, and using industry standard tools, implement the design through synthesis, floor planning, clock tree synthesis and routing.
Block level RTL design.
• Perform static timing analysis(STA) and help to identify and fix timing problems in the design
• Perform design for test (DFT) and test pattern generation (ATPG).
• Close interaction with analog/mixed signal designers.
Qualifications:
• Master's degree with at least 5 years of experience with digital RTL design and flow.
• Experience with RTL design
• Experience with one of the below area
o Synthesis,
o Timing analysis / Timing Closure
o DFT
• Knowledge of Audio processing or signal processing or SOC design is a big plus
• Knowledge of scripting languages such as Perl and Tcl is a plus.
• Good English written and verbal communication skills.
• Excellent communication and team-oriented skills.
• Self-motivated individual willing to take ownership and responsibility.
2. Digital Verification Engineer (mixed signal/SoC)
Location: Shanghai
Responsibilities:
• Verification with Verilog / System Verilog / UVM
• Setup verification testbench in module level and Chip level, define and execute verification plan with full functional coverage.
• Doing simulation in Gate Level and doing co-simulation with analog designer.
• Interact with design team to achieve design quality and meet schedule target.
• Document and review detail test plans, testbench and meet verification goals.
• Support silicon evaluation effort.
Qualifications:
• Master's degree with 5+ years of experience with SoC/Mix-signals IC verification
• Knowledge of OVM/VMM/UVM
• Knowledge of Audio processing or signal processing or SOC design is a big plus.
• Familiar with digital & mixed signal verification tools, such as NC-verilog/Verdi/Vplan.
• Familiar with Verilog/ System Verilog/ System C language.
• Knowledge of scripting languages such as Perl and Tcl is a plus.
• Good English written and verbal communication skills.
• Excellent communication and team-oriented skills.
• Self-motivated individual willing to take ownership and responsibility.
简历请发送：
ypan@invensense.com
重点：这是InvenSense在上海成立R&D 之后的第一轮社招，刚开始扩张，机会应该是相当不错的。
1.Digital RTL Design and Implementation (synthesis \ DFT \ Timing Closure) Engineer
Location: Shanghai
Responsibilities:
• Digital RTL design and implementation for mixed signal/SoC ICs
• Starting from Verilog RTL, and using industry standard tools, implement the design through synthesis, floor planning, clock tree synthesis and routing.
Block level RTL design.
• Perform static timing analysis(STA) and help to identify and fix timing problems in the design
• Perform design for test (DFT) and test pattern generation (ATPG).
• Close interaction with analog/mixed signal designers.
Qualifications:
• Master's degree with at least 5 years of experience with digital RTL design and flow.
• Experience with RTL design
• Experience with one of the below area
o Synthesis,
o Timing analysis / Timing Closure
o DFT
• Knowledge of Audio processing or signal processing or SOC design is a big plus
• Knowledge of scripting languages such as Perl and Tcl is a plus.
• Good English written and verbal communication skills.
• Excellent communication and team-oriented skills.
• Self-motivated individual willing to take ownership and responsibility.
2. Digital Verification Engineer (mixed signal/SoC)
Location: Shanghai
Responsibilities:
• Verification with Verilog / System Verilog / UVM
• Setup verification testbench in module level and Chip level, define and execute verification plan with full functional coverage.
• Doing simulation in Gate Level and doing co-simulation with analog designer.
• Interact with design team to achieve design quality and meet schedule target.
• Document and review detail test plans, testbench and meet verification goals.
• Support silicon evaluation effort.
Qualifications:
• Master's degree with 5+ years of experience with SoC/Mix-signals IC verification
• Knowledge of OVM/VMM/UVM
• Knowledge of Audio processing or signal processing or SOC design is a big plus.
• Familiar with digital & mixed signal verification tools, such as NC-verilog/Verdi/Vplan.
• Familiar with Verilog/ System Verilog/ System C language.
• Knowledge of scripting languages such as Perl and Tcl is a plus.
• Good English written and verbal communication skills.
• Excellent communication and team-oriented skills.
• Self-motivated individual willing to take ownership and responsibility.
简历请发送：
ypan@invensense.com
补充一下：
对于资历方面，牛人3年以上也可以，不一定非要5年以上