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Nvidia Shanghai ASIC-PD

时间:12-12 整理:3721RD 点击:
转自 From job_it@bbs.fudan.edu.cn
ASIC-PD team responsibilities:
1, Release gate level netlists for each physical level.
   (synthesis/formal/netlist auditor/partitioning & retiming)
2, Release constraints for each physical level.
   (understand full chip clock struture/STA clock & timing exception definition/
Timing estimation & Constraints validation/Timing budget)
3, Timing analysis,fix and signoff for each physical level.
   (Close Timing@all level,corner,mode/Close Test,IO,Async Timing/Function eco c
reation)
4, Methodology on above area
   (flow automation/Criterion define for each process)
5, We are co-working with ASIC/DFT/PR team, but we don't work on rtl code, simul
ation, dft inserstion, place&route.
Requirement:
1, Interested in backend work, especially in ASIC-PD position.
2, 2~3 years experience of ASIC, PR or ASIC-PD or 3+ years experience of ASIC-PD
.
3, Excellent English communication.
4, Special for methodology: Powerful user of perl, tcl/Familiar with SQL
5, Special for Beijing/Shenzhen ASIC-PD: 5+ years experience of ASIC-PD.
Q&A/Resumes:
jjiang@nvidia.com
※ 来源:·水木社区 newsmth.net·[FROM: 203.18.50]

看起来跟design service的timing职位比较类似啊

工作包括但不限于Timing
详情/简历 请向原贴中的公司Email 咨询

北京 招的咋样了 前几天不是说北京也要开始招吗

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