AMD(上海)SOC Team急招（内推）
时间：12-12
整理：3721RD
点击：
AMD(上海) SOC Team近期有数个Junior，Senior，Staff以及更高level的职位空缺招聘，感兴趣的同学可与我联系( mail : amd_cdc@163.com QQ:1756384832)，team内部推荐成功率会更高些哦。
职位：
1.SOC Integration Engineer : 主要涉及Synthesis/STA/LEC/MVRC/CDC/GCA等，要求一定的脚本能力(perl,shell,tcl...)。如果对上述一个或多个领域熟悉并且感兴趣的同学可以来尝试下。
2.SOC DV Engineer : 主要涉及SOC chip level的verification已经Emulation。
具体JD：
a）SOC Integration Engineer：
Integrate GPU blocks as chip based on architectural requirement.
·
Develop RTL code for macro blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
·
Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.
Requirement:
·
MS degree of EE with 1~ 8 years, or bachelor with 3~10 years working experience in ASIC Company.
·
Familiar with Verilog RTL design and has experience of large digital ASIC project.
·
Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verdi, 0in)
·
Familiar with unix/linux and scripts (tcl, perl etc.)
·
Fluent English on talking, presentation and writing documents.
Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
b)SOC DV Engineer:
The candidate will be employed in dGPU SoC level verification.
Key Job Functions:
- Understand the architecture and functionality of the chip
- Compose test plan and validation vectors to ensure functional completeness
- Develop verification environments for standalone unit testing and enhance/usethe automated regression infrastructure setup for full chip functionalverification.
- Help debug and correct functional errors in the design blocks, using logicabstraction, simulation and debug tools, based on good understanding of thearchitectural
specification, RTL and/ordevice level design of the block.
- Be responsible to mentor and coach the team for greater technical depth inFunctional areas as well as the verification methodology improvement and Infrastructureenhancements to support the design environment
Preferred Experience:
- Major in EE, CS or related with 2+ years working experiences
- Should be versatile in any one of the high level verification flow such asSV,VMM,VERA,OVM etc as well as knowledge of industry standard tools forverification
- Needs to have better understanding of Verification methodology and concepts.
- Should have good understanding of Pre-Silicon design process fromArchitecture, Design, Synthesis and Gate level Implementation till Tapeoutrelease.
- Should have excellent communication skills (both written and oral) and shouldbe able to participate cross functional engineering teams geographically.
- Familiar with Linux Environment (including shell scripting and linux gnutools)
- Proficient programming knowledge on Verilog,C++
- Knowledge on UPF based verification is a plus
- Design for verification (assertion based design strategies, code coverage,functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Strong problem solving skills
职位：
1.SOC Integration Engineer : 主要涉及Synthesis/STA/LEC/MVRC/CDC/GCA等，要求一定的脚本能力(perl,shell,tcl...)。如果对上述一个或多个领域熟悉并且感兴趣的同学可以来尝试下。
2.SOC DV Engineer : 主要涉及SOC chip level的verification已经Emulation。
具体JD：
a）SOC Integration Engineer：
Integrate GPU blocks as chip based on architectural requirement.
·
Develop RTL code for macro blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
·
Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.
Requirement:
·
MS degree of EE with 1~ 8 years, or bachelor with 3~10 years working experience in ASIC Company.
·
Familiar with Verilog RTL design and has experience of large digital ASIC project.
·
Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verdi, 0in)
·
Familiar with unix/linux and scripts (tcl, perl etc.)
·
Fluent English on talking, presentation and writing documents.
Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
b)SOC DV Engineer:
The candidate will be employed in dGPU SoC level verification.
Key Job Functions:
- Understand the architecture and functionality of the chip
- Compose test plan and validation vectors to ensure functional completeness
- Develop verification environments for standalone unit testing and enhance/usethe automated regression infrastructure setup for full chip functionalverification.
- Help debug and correct functional errors in the design blocks, using logicabstraction, simulation and debug tools, based on good understanding of thearchitectural
specification, RTL and/ordevice level design of the block.
- Be responsible to mentor and coach the team for greater technical depth inFunctional areas as well as the verification methodology improvement and Infrastructureenhancements to support the design environment
Preferred Experience:
- Major in EE, CS or related with 2+ years working experiences
- Should be versatile in any one of the high level verification flow such asSV,VMM,VERA,OVM etc as well as knowledge of industry standard tools forverification
- Needs to have better understanding of Verification methodology and concepts.
- Should have good understanding of Pre-Silicon design process fromArchitecture, Design, Synthesis and Gate level Implementation till Tapeoutrelease.
- Should have excellent communication skills (both written and oral) and shouldbe able to participate cross functional engineering teams geographically.
- Familiar with Linux Environment (including shell scripting and linux gnutools)
- Proficient programming knowledge on Verilog,C++
- Knowledge on UPF based verification is a plus
- Design for verification (assertion based design strategies, code coverage,functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Strong problem solving skills