sr。staff asic design engineer-简历发HR@hi-talent.net
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Sr ASIC Design Engineer__PCIe
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION
- Participate IP and SoC level architecture definition, derive functional and design
specifications and analyze feasibility of technical and architectures.
- Implement design with Verilog to achieve specification goals. Simulate and debug
the codes in coding stage.
- Go through the FE design flow to deliver qualified netlist. Feedback to Physical
Design team to help to close timing and check floorplan.
- Write ASIC specific part of test plan. Co-work with verification engineers to prove
functional correctness from block level to SoC level
- Support FW/SW bring-up and debugging
- Working as the technical point of contact on the ASIC area.
- Maintain design environment, solve flow issues, and develop scripts to improve flow
efficiency.
PREFERRED EXPERIENCE:
- Major in EE & CS
- Proven ASIC / SoC Design Experience (5+ years as a bachelor, 3+ years as a master).
- Must have strong background on IP development
- Must be proficient in Verilog coding, debugging and modeling
- Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO
etc.
- Must be skilled in mainstream EDA tools for design and simulation such as
ncsim/vcs, RC/DC, PT, Formality/LEC and DFT.
- Must be familiar with verification methodologies for from block level to SoC level.
- Should be familiar with shell/perl/tcl programming in linux OS.
- Should be familiar with P&R and Manufacture tech.
- Good English hearing, speaking, reading and writing capabilities.
- Will be a big plus if having mass production tape‐out experience.
- Will be a plus if having C/C++/SystemVerilog experience
Job Title:
Sr. DV Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION :
We are currently looking for an Senior Eng Design Verification Engineer who will be
responsible for all aspects of verification on next generation integrated processors chipset,
including developing DV infrastructure environment, testbenches, modeling,
assertions/checkers/monitors, test plan & test development, regressions, and
infrastructure development. Responsibility includes participating in the pre-silicon blocks,
chip, multi-chip and system level verification strategy:
- Verification of Graphic North Bridge design using complex DV environment C/C++,
SystemVeilog, OVM, SystemC, Verilog - Infrastructure development
- Experience in use of front end CAD tools Synopsys (VCS, )
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled, multiple sites North
America and Asia
- Flexible in terms of responsibilities and hours.
PREFERRED EXPERIENCE:
- Bachelor/Master in Electrical/Computer Engineering.
- Strong C and C++ software development and scripting languages (Perl, C Shell,
Makefile, …) experience.
- Good knowledge of SystemVerilog and OVM is desirable.
- 3+ years experience in Verification in a large scale ASIC design environment.
Strong background with hardware verification methodologies such as coverage-based
verification methodology with the use of hardware assertions (PSL or SVA).
Strong analytical thinking skills, excellent attention to detail, and good coding skills
are required.
Must be organized, enthusiastic self-starter and have good communication skills and
the ability and desire to work as a team.
Job Title:
Staff/Sr/ GPU ASIC Integration Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION
- Responsible for the execution of the chip integration process. This will include
design, implementation and execution of the flow that starts with RTL code and ends
with the delivery of a netlist package ready for physical design.
- Responsible for synthesis, netlist generation, timing and logical equivalency checks,
and timing constraint management. In this role you will get to experience many
aspects of the chip design process working as the bridge between the logic design &
verification group and the physical design group. Every piece of the design that will
make it into the final chip will at some point pass through your virtual hands.
PREFERRED EXPERIENCE:
1. Master/Bachelor Degree in electrical engineering with years of digital circuit design and
logic design experience;
2. Familiar with Verilog HDL coding and ASIC Frond-End flow
3. Familiar with unix/linux and scripts (tcl, perl etc.)
4. Strong task-based organization skill
5. Computer Architecture and computer Arithmatic
6. Computer Graphic Basic knowledge(a plus)
7. PCI/PCI-e experience(a plus)
贵司有招聘需求的，欢迎和我联系；
如果你和你朋友有需要看工作机会的，发简历给我Jane-Jin@Hi-Talent.net
Best Regards,
Jane.Jin
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯相会企业管理咨询有限公司
Mob: 15921265928
Skype: ScarlettJaneJin
E-Mail: Jane-Jin@Hi-Talent.net
QQ: 1687562641
Blog: http://blog.sina.com.cn/u/1716864892
Weibo: http://weibo.com/u/1716864892
Linkedin: jj_seu@hotmail.com
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION
- Participate IP and SoC level architecture definition, derive functional and design
specifications and analyze feasibility of technical and architectures.
- Implement design with Verilog to achieve specification goals. Simulate and debug
the codes in coding stage.
- Go through the FE design flow to deliver qualified netlist. Feedback to Physical
Design team to help to close timing and check floorplan.
- Write ASIC specific part of test plan. Co-work with verification engineers to prove
functional correctness from block level to SoC level
- Support FW/SW bring-up and debugging
- Working as the technical point of contact on the ASIC area.
- Maintain design environment, solve flow issues, and develop scripts to improve flow
efficiency.
PREFERRED EXPERIENCE:
- Major in EE & CS
- Proven ASIC / SoC Design Experience (5+ years as a bachelor, 3+ years as a master).
- Must have strong background on IP development
- Must be proficient in Verilog coding, debugging and modeling
- Must be skilled in ASIC design flow, such as synthesis, DFT, timing analysis, ECO
etc.
- Must be skilled in mainstream EDA tools for design and simulation such as
ncsim/vcs, RC/DC, PT, Formality/LEC and DFT.
- Must be familiar with verification methodologies for from block level to SoC level.
- Should be familiar with shell/perl/tcl programming in linux OS.
- Should be familiar with P&R and Manufacture tech.
- Good English hearing, speaking, reading and writing capabilities.
- Will be a big plus if having mass production tape‐out experience.
- Will be a plus if having C/C++/SystemVerilog experience
Job Title:
Sr. DV Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION :
We are currently looking for an Senior Eng Design Verification Engineer who will be
responsible for all aspects of verification on next generation integrated processors chipset,
including developing DV infrastructure environment, testbenches, modeling,
assertions/checkers/monitors, test plan & test development, regressions, and
infrastructure development. Responsibility includes participating in the pre-silicon blocks,
chip, multi-chip and system level verification strategy:
- Verification of Graphic North Bridge design using complex DV environment C/C++,
SystemVeilog, OVM, SystemC, Verilog - Infrastructure development
- Experience in use of front end CAD tools Synopsys (VCS, )
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled, multiple sites North
America and Asia
- Flexible in terms of responsibilities and hours.
PREFERRED EXPERIENCE:
- Bachelor/Master in Electrical/Computer Engineering.
- Strong C and C++ software development and scripting languages (Perl, C Shell,
Makefile, …) experience.
- Good knowledge of SystemVerilog and OVM is desirable.
- 3+ years experience in Verification in a large scale ASIC design environment.
Strong background with hardware verification methodologies such as coverage-based
verification methodology with the use of hardware assertions (PSL or SVA).
Strong analytical thinking skills, excellent attention to detail, and good coding skills
are required.
Must be organized, enthusiastic self-starter and have good communication skills and
the ability and desire to work as a team.
Job Title:
Staff/Sr/ GPU ASIC Integration Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION
- Responsible for the execution of the chip integration process. This will include
design, implementation and execution of the flow that starts with RTL code and ends
with the delivery of a netlist package ready for physical design.
- Responsible for synthesis, netlist generation, timing and logical equivalency checks,
and timing constraint management. In this role you will get to experience many
aspects of the chip design process working as the bridge between the logic design &
verification group and the physical design group. Every piece of the design that will
make it into the final chip will at some point pass through your virtual hands.
PREFERRED EXPERIENCE:
1. Master/Bachelor Degree in electrical engineering with years of digital circuit design and
logic design experience;
2. Familiar with Verilog HDL coding and ASIC Frond-End flow
3. Familiar with unix/linux and scripts (tcl, perl etc.)
4. Strong task-based organization skill
5. Computer Architecture and computer Arithmatic
6. Computer Graphic Basic knowledge(a plus)
7. PCI/PCI-e experience(a plus)
贵司有招聘需求的，欢迎和我联系；
如果你和你朋友有需要看工作机会的，发简历给我Jane-Jin@Hi-Talent.net
Best Regards,
Jane.Jin
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯相会企业管理咨询有限公司
Mob: 15921265928
Skype: ScarlettJaneJin
E-Mail: Jane-Jin@Hi-Talent.net
QQ: 1687562641
Blog: http://blog.sina.com.cn/u/1716864892
Weibo: http://weibo.com/u/1716864892
Linkedin: jj_seu@hotmail.com