AMD 上海 后端热招内部推荐
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内推，下面要求不一定全要满足，根据level不同要求也不同有兴趣可以发简历到
1176811755@qq.com 或者qq咨询
Position Title Senior /MTS/SMTS Engineer of Physical Design
Organization Shanghai R&D Center Function
Location Shanghai, China Rep/Add Add
Job Description:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.
Job Requirement:
MSEE with 8+ years or Bachelor with 10+ years of industrial experience in ASIC design
5+ years or more years of experience in physical design of deep submicron digital ASIC chips
Hands on experience in large scale ASIC chip physical design
Knowledgeable in all aspects of deep submicron ASIC design flow
Successfully gone through several complete product development cycles
Demonstrate strong leadership and work well with cross-functional teams
Good listening, writing and speaking English
Good communication skills, strong interpersonal skills and the flexibility
Dedicated, hard working and good team player
Familiar with Back-End (physical design) EDA tools
Familiar with Front-End EDA tools is a plus
Familiar with Unix/Linux environment and good at scripts
1176811755@qq.com 或者qq咨询
Position Title Senior /MTS/SMTS Engineer of Physical Design
Organization Shanghai R&D Center Function
Location Shanghai, China Rep/Add Add
Job Description:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.
Job Requirement:
MSEE with 8+ years or Bachelor with 10+ years of industrial experience in ASIC design
5+ years or more years of experience in physical design of deep submicron digital ASIC chips
Hands on experience in large scale ASIC chip physical design
Knowledgeable in all aspects of deep submicron ASIC design flow
Successfully gone through several complete product development cycles
Demonstrate strong leadership and work well with cross-functional teams
Good listening, writing and speaking English
Good communication skills, strong interpersonal skills and the flexibility
Dedicated, hard working and good team player
Familiar with Back-End (physical design) EDA tools
Familiar with Front-End EDA tools is a plus
Familiar with Unix/Linux environment and good at scripts
从NV招些人来，然后在跑些人去NV，互补下