有通信方向 背景的senior IC验证看过来罗~~ 新加坡的工作机会！
时间：12-12
整理：3721RD
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Senior Digital Verification Engineer
The position is base on Singapore.
1. 5+ years Experienced ASIC, SOC design verification expert with block to chip level verification experience. Familiar with verification flow and worked on testbench, testplan, test execution and coverage closure, tape out and silicon validation.
2. Hands on experience with one of the modern verification methodologies such as UVM, VMM, OVM, and familiar with constraint random based verification, including OOP, functional coverage, assertion checker/coverage and virtual interface.
3. Proficient in HVL(hardware verification language) such as System Verilog, Verilog, System C or Vera.
4. Knowledge and background in networking protocols such as Ethernet, PCIe, TCP/IP, Serdes, MAC and PHY are preferred.
5. Experience on networking IC design and verification is preferred, especially ethernet switch, PHY, traffic manager, network processor, switch fabric and memory sub system projects.
6. The following skills are not required but under consideration: Perl, TLM, DPI, XACT, XML, PHP, mySQL.
7. Emulation, FPGA verification and IXIA, SmartBit debugging experience are a plus.
The position is base on Singapore.
1. 5+ years Experienced ASIC, SOC design verification expert with block to chip level verification experience. Familiar with verification flow and worked on testbench, testplan, test execution and coverage closure, tape out and silicon validation.
2. Hands on experience with one of the modern verification methodologies such as UVM, VMM, OVM, and familiar with constraint random based verification, including OOP, functional coverage, assertion checker/coverage and virtual interface.
3. Proficient in HVL(hardware verification language) such as System Verilog, Verilog, System C or Vera.
4. Knowledge and background in networking protocols such as Ethernet, PCIe, TCP/IP, Serdes, MAC and PHY are preferred.
5. Experience on networking IC design and verification is preferred, especially ethernet switch, PHY, traffic manager, network processor, switch fabric and memory sub system projects.
6. The following skills are not required but under consideration: Perl, TLM, DPI, XACT, XML, PHP, mySQL.
7. Emulation, FPGA verification and IXIA, SmartBit debugging experience are a plus.
有意向的联系我哦~~~ 进一步聊。 QQ：2251638853 Email:2251638853@qq.com
感觉像MTK
IC验证的 兄台们 看过来看过来····
薪水大概有多少，比如硕士三年大概的范围是多少？
英语要求不高的。。。。要求工作经验至少5年的哦。
traffic manager 怎么理解啊？什么模块会用到traffic manager啊？请教……
都太贵
马上就都淘汰了
以后np/tm一个芯片搞定
集成的早就做了，边缘或接入应用。核心的还是得分开做。
边缘和接入的带宽低，当然好做
核心的最多几百T的容量，怎么可能一个片子做
这类片子没几家做了，商用流通的我就知道bcom还有点，其他都是自己做自己用
本身核心路由器，也就思科，juniper算赚钱的，华为的核心路由器刚开始赚钱
由棱镜门想到，此类路由网络核心芯片，不能用美国的，以后几年可能市场大，赞该公司有预见性