AMD北京上海继续招人，新增CAD职位
时间：12-12
整理：3721RD
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dhk0307@163.com
北京职位如下：
ASIC Engineer for Chip Integration (MTS/Sr. Eng)
MM Senior/MTS DV
Senior/MTS DFT
FCH MTS/Sr/SMTS design entineer
FCH MTS/Sr/SMTS DV
FCH MTS/Sr/SMTS SOC
OSS MTS/Senior system verification engineer
Sr./MTS Physical Design Engineer
Sr. ASIC CAD Engineer - Timing
Sr. ASIC CAD Engineer – FCFP/TDFP
ASIC Engineer for Chip Integration
Responsibility:
Integrate functional IPs into SoC per architectural requirement.
Develop RTL code for macro blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
Participate in making functional/technology based chip targets in timing, area, power. Develop timing constraint, power intent spec accordingly.
Synthesis and deliver qualified netlist, cowork with PD to settle chip floorplan and achieve timing closure.
Requirement:
major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences in ASIC Company.
familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power ) and usage of related EDA tools.
Familiar with script languages((tcl, perl etc.) in unix/linux.
Good written and spoken English.
Good communication skills and be able to work both independently and in a team
Job Title: Senior Design Verification Engineer for SoC
City/Town: Beijing
Country: China
Job Description: Responsibility:
We are currently looking for Staff Engineers who will be responsible for all aspects of verification on next generation integrated processors (CPU + GPU + Multi Media), including developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy:
- Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.
- Develop System Verilog (OVM) random sequences and methods.
- Maintain and Interface with existing random generators, models and APIs
- Integration of random modules to various testbenches.
- Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
- Flexible in terms of responsibilities and hours.
Requirement:
- 3+ years experience with Master degree or 5+ years experience with Bachelor degree.
- Complex ASIC/SOC Design Verification, direct experience in SOC or Processor (GPU or CPU) or Industry bus standard (PCI-e, MC, HT) or multimedia/video is preferred.
- Good knowledge of SystemVerilog and OVM is a plus.
- Good knowledge of Verilog/C/C++/System C/SystemVerilog.
- Verification insights into random techniques.
- Verification of large scale ASICs.
- Experience in power verification is an asset.
- Verification of Virtualization Components is an asset.
- C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
- Background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).
Member of technical staff for IC design verification (MTS DV)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design verification.
The candidate must have:
1.deep understanding on ASIC/SOC design flow
2.Excellent knowledge of design verification methodology, such as VMM or OVM.
3.Solid experiences with simulation model creation and the testbench build
4.Strong RTL coding with Verilog
5.Strong C/C++ software development experiences
6.Be good at scripting language, such as Perl, C shell, Makefile.
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
Responsibility:
The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge design. The candidate will provide the technical leadership to the DV team for the new Southbridge project. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
Sr. PD
JOB TITLE:
Sr. Physical Design Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc.
PREFERRED EXPERIENCE:
1. MSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASIC design
2. Expertise in place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, timing closure.
3. Successfully gone through complete product development cycle. Good analytical and debugging skills
4. Good listening, writing and speaking English.
5. Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player
6. Familiar with Back-End (physical design) EDA tools (synopsys,cadence,magma)
7. Familiar with Front-End EDA tools or circuit design is a plus
8. Familiar with Unix/Linux environment and good at scripts
Member of technical staff for Physical Design(MTS PD)
Job Description:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place& route, physical verification etc. The individual is expected to be an expert in at least one PD area and provide technically leadership to the engineering team.
Requirements:
1. MSEE with 6+ years or Bachelor with 8+ years of industrial experience in ASIC design
2. 3+ years or more years of experience in physical design of deep submicron digital ASIC chips
3. Hands on experience in large scale ASIC chip physical design
4. Knowledgeable in all aspects of deep submicron ASIC design flow
5. Successfully gone through several complete product development cycles
6. Demonstrate leadership and work well with cross-functional teams
7. Good listening, writing and speaking English
8. Good communication skills, strong interpersonal skills and the flexibility
9. Dedicated, hard working and good team player
10. Familiar with Back-End (physical design) EDA tools
11. Familiar with Front-End EDA tools is a plus
12. Familiar with Unix/Linux environment and good at scripts
Sr. Design Engineer – DFT
Job Description:
Qualified candidate will perform some or all functions below:
1. Participate in SOC full Chip DFT feature and architecture definition
2. Responsible for DFT specification generation and review
3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
4. Perform verification on all DFT structures
5. Generate DFT related timing constraints and work with PD team for timing closure
6. Generate and verify DFT structural patterns and functional patterns
7. Participate in ATE bring-up and debug the DFT patterns on ATE
8. Design and implement other DFX (debug, characterization, yield etc) logics
Requirements/Qualifications:
- BS in EE & CS. MS preferred.
- Hands on working experience on ASIC DFT design and verification
- Familiar with entire ASIC design flow
- Experience with micro processor design a big plus
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
Member of technical staff for Design Engineer-DFT
Job Description:
Qualified candidate will perform some or all functions below:
1. Participate in SOC full Chip DFT feature and architecture definition
2. Responsible for DFT specification generation and review
3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
4. Perform verification on all DFT structures
5. Generate DFT related timing constraints and work with PD team for timing closure
6. Generate and verify DFT structural patterns and functional patterns
7. Participate in ATE bring-up and debug the DFT patterns on ATE
8. Design and implement other DFX (debug, characterization, yield etc) logics
Requirements/Qualifications:
- BS in EE & CS. MS preferred.
- Hands on working experience on ASIC DFT design and verification
- Familiar with entire ASIC design flow
- Experience with micro processor design a big plus
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
Member of technical staff for IC design engineering (MTS DE)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc.
Senior engineer for IC design engineering (Sr. DE)
Requirements:
The candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5 years experience in digital ASIC/SOC design engineering. The candidate should have good understanding on ASIC/SOC design flow and must be proficient in two or more of the following skill sets:
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Senior member of technical staff for IC design engineering (SMTS DE)
Requirements:
The candidate is preferred to be MSEE with minimum of 9 years, or BSEE with minimum of 11 years experience in digital ASIC/SOC design engineering.
The candidate should have extremely deep understanding on ASIC/SOC design flow.
It is a must that the candidate has two or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge outside his or her area of expertise, driving execution of quality and timely project performance, capability to solve complex, novel and no-recurring problems, capability to initiate significant changes and lead development & implementation, and decision-making on most critical technical areas.
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC projects. The role will include technical leading on multiple products or product line, coaching and mentoring less experienced staff and influencing others as a strong technical leader.
Member of technical staff for IC design verification (MTS DV)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design verification.
The candidate must have:
1.deep understanding on ASIC/SOC design flow
2.Excellent knowledge of design verification methodology, such as VMM or OVM.
3.Solid experiences with simulation model creation and the testbench build
4.Strong RTL coding with Verilog
5.Strong C/C++ software development experiences
6.Be good at scripting language, such as Perl, C shell, Makefile.
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
Responsibility:
The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge design. The candidate will provide the technical leadership to the DV team for the new Southbridge project. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
Member of technical staff for IC SOC engineering (MTS SOC)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.
The candidate should have deep understanding on ASIC/SOC design flow and must be proficient in quite a lot of following skill sets:
1.RTL(verilog) coding and style checking
2.scripts based on makefile, perl, TCL or csh/tcsh
3.clock-domain-cross checking
4.logic synthesis or physical Synthesis
5.static timing analysis
6.logic equivalency checking
7.ECO(engineering change order)
8.top level integration, floor planning, pad-ring design
9.clock distribution
10.design for test, design for debug or design for power
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, synthesis, timing closure, etc.
Senior engineer for IC design verification (Sr. DV)
Requirements:
The candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5 years experience in digital ASIC/SOC design verification. The candidate should have good understanding on ASIC/SOC design flow and should have:
1.Good knowledge of design verification methodology, such as VMM or OVM.
2.Many experiences with simulation model creation and the testbench build
3.Strong RTL coding with Verilog and familiar with front-end design flow
4.Strong C/C++ software development experiences
5.Be familiar with scripting language, such as Perl, C shell, Makefile.
It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility:
The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
Senior engineer for IC SOC engineering (Sr. SOC)
Requirements:
The candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5 years experience in digital ASIC/SOC design engineering. The candidate should have good understanding on ASIC/SOC design flow and must be proficient in two or more of the following skill sets:
1.RTL(verilog) coding and style checking
2.scripts based on makefile, perl, TCL or csh/tcsh
3.clock-domain-cross checking
4.dynamic logic simulation or post-layout simulation
5.logic synthesis or physical Synthesis
6.static timing analysis
7.logic equivalency checking
8.ECO(engineering change order)
9.top level integration, floor planning, pad-ring design
10.clock distribution
11.design for test, design for debug or design for power
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: specification, top level SOC design tasks, synthesis, timing closure, etc.
Senior member of technical staff for IC design verification (SMTS DV)
Requirements:
The candidate is preferred to be MSEE with minimum of 9 years, or BSEE with minimum of 11 years experience in digital ASIC/SOC design verification.
The candidate must have:
1.Deep understanding on ASIC/SOC design flow
2.Excellent knowledge of design verification methodology, such as VMM or OVM.
3.Solid experiences with simulation model creation and the testbench build
4.Strong RTL coding with Verilog
5.Strong C/C++ software development experiences
6.Be good at scripting language, such as Perl, C shell, Makefile.
It is a must that the candidate has two or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge outside his or her area of expertise, driving execution of quality and timely project performance, capability to solve complex, novel and no-recurring problems, capability to initiate significant changes and lead development & implementation, and decision-making on most critical technical areas.
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
Responsibility:
The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC projects. The role will include technical leading on multiple products or product line, coaching and mentoring less experienced staff and influencing others as a strong technical leader.
Senior member of technical staff for IC SOC engineering (SMTS SOC)
Requirements:
The candidate is preferred to be MSEE with minimum of 9 years, or BSEE with minimum of 11 years experience in digital ASIC/SOC design engineering.
The candidate should have extremely deep understanding on ASIC/SOC design flow and show his/her expertise on quite a lot of following skill sets:
1.RTL(verilog) coding and style checking
2.scripts based on makefile, perl, TCL or csh/tcsh
3.clock-domain-cross checking
4.dynamic logic simulation or post-layout simulation
5.logic synthesis or physical Synthesis
6.static timing analysis
7.logic equivalency checking
8.ECO(engineering change order)
9.top level integration, floor planning, pad-ring design
10.clock distribution
11.design for test, design for debug or design for power
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge outside his or her area of expertise, driving execution of quality and timely project performance, capability to solve complex, novel and no-recurring problems, capability to initiate significant changes and lead development & implementation, and decision-making on most critical technical areas.
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC projects. The role will include technical leading on multiple products or product line, coaching and mentoring less experienced staff and influencing others as a strong technical leader.
OSS MTS/Senior system verification engineer
Requirements:
1) MS or above of CS, EE or related fields.
2) A solid foundation of Computer Architecture and Operating system
3) Several years(3+ for senior, 5+ for MTS) work experience on Verification or Design.
4) Proficient on C++ and familiar with Verilog, or proficient on Verilog and familiar with C++
5) Familiar with Perl or other script language
6) Fluency in English
7) Good at communication
Position Title Senior ASIC CAD Engineer - Timing
Job Description:
Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD global teams.
Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge products
Technical support and programming
Interface with EDA venders on technology
Requirement:
major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences
extensive Primetime experience is a must
extensive script experience is a must (Perl/Python/TCL), C programming experience is also OK
analytic skills and problem solving skills
good English in reading/writing
design experience or Synthesis experience with DC/RC is a plus
good English is speaking is a plus
Position Title Senior ASIC CAD Engineer – FCFP/TDFP
Job Description:
Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD global teams.
Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge products
Technical support and programming
Interface with EDA venders on technology
Requirement:
major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences
Good understanding of modern large chip design flow: Construction and verification.
Experience with floorplanning and/or P&R tools (Synopsys ICC, Cadence First Encounter)
Work experience with PD design or with support of PD design team.
Good working knowledge of python or PERL, unix cshell, programming.
Good problem solving skills.
Good communication skills - a must.
Proficiency in English (Speaking and writing) is very important in order to communicate with the team in US and other design team world-wide.
Fast learner.
Very nice to have:
Experience with Cadence First Encounter (also called EDI) for floorplanning
Work experience in developing (CAD) software.
Experience working with teams in multi international sites.
Experience with OA data base.
※ FROM: 163.181.251]
※ 来源:·水木社区 http://newsmth.net·[FROM: 114.66.8]
dhk0307@163.com
北京职位如下：
ASIC Engineer for Chip Integration (MTS/Sr. Eng)
MM Senior/MTS DV
Senior/MTS DFT
FCH MTS/Sr/SMTS design entineer
FCH MTS/Sr/SMTS DV
FCH MTS/Sr/SMTS SOC
OSS MTS/Senior system verification engineer
Sr./MTS Physical Design Engineer
Sr. ASIC CAD Engineer - Timing
Sr. ASIC CAD Engineer – FCFP/TDFP
ASIC Engineer for Chip Integration
Responsibility:
Integrate functional IPs into SoC per architectural requirement.
Develop RTL code for macro blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
Participate in making functional/technology based chip targets in timing, area, power. Develop timing constraint, power intent spec accordingly.
Synthesis and deliver qualified netlist, cowork with PD to settle chip floorplan and achieve timing closure.
Requirement:
major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences in ASIC Company.
familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power ) and usage of related EDA tools.
Familiar with script languages((tcl, perl etc.) in unix/linux.
Good written and spoken English.
Good communication skills and be able to work both independently and in a team
Job Title: Senior Design Verification Engineer for SoC
City/Town: Beijing
Country: China
Job Description: Responsibility:
We are currently looking for Staff Engineers who will be responsible for all aspects of verification on next generation integrated processors (CPU + GPU + Multi Media), including developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy:
- Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.
- Develop System Verilog (OVM) random sequences and methods.
- Maintain and Interface with existing random generators, models and APIs
- Integration of random modules to various testbenches.
- Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
- Flexible in terms of responsibilities and hours.
Requirement:
- 3+ years experience with Master degree or 5+ years experience with Bachelor degree.
- Complex ASIC/SOC Design Verification, direct experience in SOC or Processor (GPU or CPU) or Industry bus standard (PCI-e, MC, HT) or multimedia/video is preferred.
- Good knowledge of SystemVerilog and OVM is a plus.
- Good knowledge of Verilog/C/C++/System C/SystemVerilog.
- Verification insights into random techniques.
- Verification of large scale ASICs.
- Experience in power verification is an asset.
- Verification of Virtualization Components is an asset.
- C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
- Background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).
Member of technical staff for IC design verification (MTS DV)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design verification.
The candidate must have:
1.deep understanding on ASIC/SOC design flow
2.Excellent knowledge of design verification methodology, such as VMM or OVM.
3.Solid experiences with simulation model creation and the testbench build
4.Strong RTL coding with Verilog
5.Strong C/C++ software development experiences
6.Be good at scripting language, such as Perl, C shell, Makefile.
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
Responsibility:
The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge design. The candidate will provide the technical leadership to the DV team for the new Southbridge project. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
Sr. PD
JOB TITLE:
Sr. Physical Design Engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc.
PREFERRED EXPERIENCE:
1. MSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASIC design
2. Expertise in place and routing, signal integrity, power analysis, CTS design, DFT, design rule and connectivity verification, timing closure.
3. Successfully gone through complete product development cycle. Good analytical and debugging skills
4. Good listening, writing and speaking English.
5. Good communication skills, strong interpersonal skills and the flexibility. Dedicated, hard working and good team player
6. Familiar with Back-End (physical design) EDA tools (synopsys,cadence,magma)
7. Familiar with Front-End EDA tools or circuit design is a plus
8. Familiar with Unix/Linux environment and good at scripts
Member of technical staff for Physical Design(MTS PD)
Job Description:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place& route, physical verification etc. The individual is expected to be an expert in at least one PD area and provide technically leadership to the engineering team.
Requirements:
1. MSEE with 6+ years or Bachelor with 8+ years of industrial experience in ASIC design
2. 3+ years or more years of experience in physical design of deep submicron digital ASIC chips
3. Hands on experience in large scale ASIC chip physical design
4. Knowledgeable in all aspects of deep submicron ASIC design flow
5. Successfully gone through several complete product development cycles
6. Demonstrate leadership and work well with cross-functional teams
7. Good listening, writing and speaking English
8. Good communication skills, strong interpersonal skills and the flexibility
9. Dedicated, hard working and good team player
10. Familiar with Back-End (physical design) EDA tools
11. Familiar with Front-End EDA tools is a plus
12. Familiar with Unix/Linux environment and good at scripts
Sr. Design Engineer – DFT
Job Description:
Qualified candidate will perform some or all functions below:
1. Participate in SOC full Chip DFT feature and architecture definition
2. Responsible for DFT specification generation and review
3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
4. Perform verification on all DFT structures
5. Generate DFT related timing constraints and work with PD team for timing closure
6. Generate and verify DFT structural patterns and functional patterns
7. Participate in ATE bring-up and debug the DFT patterns on ATE
8. Design and implement other DFX (debug, characterization, yield etc) logics
Requirements/Qualifications:
- BS in EE & CS. MS preferred.
- Hands on working experience on ASIC DFT design and verification
- Familiar with entire ASIC design flow
- Experience with micro processor design a big plus
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
Member of technical staff for Design Engineer-DFT
Job Description:
Qualified candidate will perform some or all functions below:
1. Participate in SOC full Chip DFT feature and architecture definition
2. Responsible for DFT specification generation and review
3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
4. Perform verification on all DFT structures
5. Generate DFT related timing constraints and work with PD team for timing closure
6. Generate and verify DFT structural patterns and functional patterns
7. Participate in ATE bring-up and debug the DFT patterns on ATE
8. Design and implement other DFX (debug, characterization, yield etc) logics
Requirements/Qualifications:
- BS in EE & CS. MS preferred.
- Hands on working experience on ASIC DFT design and verification
- Familiar with entire ASIC design flow
- Experience with micro processor design a big plus
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
Member of technical staff for IC design engineering (MTS DE)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc.
Senior engineer for IC design engineering (Sr. DE)
Requirements:
The candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5 years experience in digital ASIC/SOC design engineering. The candidate should have good understanding on ASIC/SOC design flow and must be proficient in two or more of the following skill sets:
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Senior member of technical staff for IC design engineering (SMTS DE)
Requirements:
The candidate is preferred to be MSEE with minimum of 9 years, or BSEE with minimum of 11 years experience in digital ASIC/SOC design engineering.
The candidate should have extremely deep understanding on ASIC/SOC design flow.
It is a must that the candidate has two or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge outside his or her area of expertise, driving execution of quality and timely project performance, capability to solve complex, novel and no-recurring problems, capability to initiate significant changes and lead development & implementation, and decision-making on most critical technical areas.
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC projects. The role will include technical leading on multiple products or product line, coaching and mentoring less experienced staff and influencing others as a strong technical leader.
Member of technical staff for IC design verification (MTS DV)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design verification.
The candidate must have:
1.deep understanding on ASIC/SOC design flow
2.Excellent knowledge of design verification methodology, such as VMM or OVM.
3.Solid experiences with simulation model creation and the testbench build
4.Strong RTL coding with Verilog
5.Strong C/C++ software development experiences
6.Be good at scripting language, such as Perl, C shell, Makefile.
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
Responsibility:
The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for Southbridge design. The candidate will provide the technical leadership to the DV team for the new Southbridge project. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
Member of technical staff for IC SOC engineering (MTS SOC)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.
The candidate should have deep understanding on ASIC/SOC design flow and must be proficient in quite a lot of following skill sets:
1.RTL(verilog) coding and style checking
2.scripts based on makefile, perl, TCL or csh/tcsh
3.clock-domain-cross checking
4.logic synthesis or physical Synthesis
5.static timing analysis
6.logic equivalency checking
7.ECO(engineering change order)
8.top level integration, floor planning, pad-ring design
9.clock distribution
10.design for test, design for debug or design for power
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, synthesis, timing closure, etc.
Senior engineer for IC design verification (Sr. DV)
Requirements:
The candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5 years experience in digital ASIC/SOC design verification. The candidate should have good understanding on ASIC/SOC design flow and should have:
1.Good knowledge of design verification methodology, such as VMM or OVM.
2.Many experiences with simulation model creation and the testbench build
3.Strong RTL coding with Verilog and familiar with front-end design flow
4.Strong C/C++ software development experiences
5.Be familiar with scripting language, such as Perl, C shell, Makefile.
It is a plus if the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility:
The successful candidate will apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC design. He/She should be able to work independently on various DV tasks and providing technical guidance to the DV team. The candidate would involve technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup.
Senior engineer for IC SOC engineering (Sr. SOC)
Requirements:
The candidate is preferred to be MSEE with minimum of 3 years, or BSEE with minimum of 5 years experience in digital ASIC/SOC design engineering. The candidate should have good understanding on ASIC/SOC design flow and must be proficient in two or more of the following skill sets:
1.RTL(verilog) coding and style checking
2.scripts based on makefile, perl, TCL or csh/tcsh
3.clock-domain-cross checking
4.dynamic logic simulation or post-layout simulation
5.logic synthesis or physical Synthesis
6.static timing analysis
7.logic equivalency checking
8.ECO(engineering change order)
9.top level integration, floor planning, pad-ring design
10.clock distribution
11.design for test, design for debug or design for power
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, imaginative thinking and sophisticated analytical techniques, self-driven for quality and timely result, capability to solve complex problems and makes some modifications to standard methods and decision-making on important technical areas.
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: specification, top level SOC design tasks, synthesis, timing closure, etc.
Senior member of technical staff for IC design verification (SMTS DV)
Requirements:
The candidate is preferred to be MSEE with minimum of 9 years, or BSEE with minimum of 11 years experience in digital ASIC/SOC design verification.
The candidate must have:
1.Deep understanding on ASIC/SOC design flow
2.Excellent knowledge of design verification methodology, such as VMM or OVM.
3.Solid experiences with simulation model creation and the testbench build
4.Strong RTL coding with Verilog
5.Strong C/C++ software development experiences
6.Be good at scripting language, such as Perl, C shell, Makefile.
It is a must that the candidate has two or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge outside his or her area of expertise, driving execution of quality and timely project performance, capability to solve complex, novel and no-recurring problems, capability to initiate significant changes and lead development & implementation, and decision-making on most critical technical areas.
Hands-on lab experience is another plus, able to understand and/or use the use scopes, logic analyzers, has knowledge or skill of board-level lab debugging.
Responsibility:
The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC projects. The role will include technical leading on multiple products or product line, coaching and mentoring less experienced staff and influencing others as a strong technical leader.
Senior member of technical staff for IC SOC engineering (SMTS SOC)
Requirements:
The candidate is preferred to be MSEE with minimum of 9 years, or BSEE with minimum of 11 years experience in digital ASIC/SOC design engineering.
The candidate should have extremely deep understanding on ASIC/SOC design flow and show his/her expertise on quite a lot of following skill sets:
1.RTL(verilog) coding and style checking
2.scripts based on makefile, perl, TCL or csh/tcsh
3.clock-domain-cross checking
4.dynamic logic simulation or post-layout simulation
5.logic synthesis or physical Synthesis
6.static timing analysis
7.logic equivalency checking
8.ECO(engineering change order)
9.top level integration, floor planning, pad-ring design
10.clock distribution
11.design for test, design for debug or design for power
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge outside his or her area of expertise, driving execution of quality and timely project performance, capability to solve complex, novel and no-recurring problems, capability to initiate significant changes and lead development & implementation, and decision-making on most critical technical areas.
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC projects. The role will include technical leading on multiple products or product line, coaching and mentoring less experienced staff and influencing others as a strong technical leader.
OSS MTS/Senior system verification engineer
Requirements:
1) MS or above of CS, EE or related fields.
2) A solid foundation of Computer Architecture and Operating system
3) Several years(3+ for senior, 5+ for MTS) work experience on Verification or Design.
4) Proficient on C++ and familiar with Verilog, or proficient on Verilog and familiar with C++
5) Familiar with Perl or other script language
6) Fluency in English
7) Good at communication
Position Title Senior ASIC CAD Engineer - Timing
Job Description:
Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD global teams.
Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge products
Technical support and programming
Interface with EDA venders on technology
Requirement:
major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences
extensive Primetime experience is a must
extensive script experience is a must (Perl/Python/TCL), C programming experience is also OK
analytic skills and problem solving skills
good English in reading/writing
design experience or Synthesis experience with DC/RC is a plus
good English is speaking is a plus
Position Title Senior ASIC CAD Engineer – FCFP/TDFP
Job Description:
Participate in the design and implementation of the leading edge, front-to-back ASIC design flow which covers logical and physical implementation and analysis of complex devices that integrate multiple cores and IP’s from organizations with AMD global teams.
Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge products
Technical support and programming
Interface with EDA venders on technology
Requirement:
major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences
Good understanding of modern large chip design flow: Construction and verification.
Experience with floorplanning and/or P&R tools (Synopsys ICC, Cadence First Encounter)
Work experience with PD design or with support of PD design team.
Good working knowledge of python or PERL, unix cshell, programming.
Good problem solving skills.
Good communication skills - a must.
Proficiency in English (Speaking and writing) is very important in order to communicate with the team in US and other design team world-wide.
Fast learner.
Very nice to have:
Experience with Cadence First Encounter (also called EDI) for floorplanning
Work experience in developing (CAD) software.
Experience working with teams in multi international sites.
Experience with OA data base.
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