IBM Layout Design Engineer(Chip Design Center)
时间：12-12
整理：3721RD
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IBM Layout Design Engineer
Job Scopes & Responsibilities:
IBM Layout Design Engineers are working on cutting-edge Digital Custom and Mixed-Signal Circuit IP layout design (e.g. High-Speed Interface, Memory Array, PLL, High-Speed SerDes,Advanced Processor, etc...) on SOI 45nm, 32nm, and beyond semiconductor technologies for IBM ASIC and Foundry clients. The candidates will be closely working with worldwide design
teams and responsible for/participate in:
(1) Perform layout design which includes low level IP blocks as well as IP layout integration which minimizes area, provides high reliability, DRC/LVS clean, and meets all committed schedules.
(2) Develop initial floorplan and power/ground distribution.
(3) Interact closely with circuit designers to assure all design 0bjectives are being met.
(4) Deliver on schedule, all physical design rules which pass DRC/LVS.
(5) Perform yield and reliability assessment of the physical design.
Job Requirements:
(1) EE or related background in digital/analog circuit design areas.
(2) Industry experience (1-2 years as entry level, more is preferable) in related areas.
(3) Solid knowledge in deep submicron or nanometer CMOS device, process and technology.
(4) Solid knowledge and understanding of DRC/LVS and extraction procedures.
(5) Solid knowledge in relevant EDA tools and environment, such as Cadence, Synopsys and Mentor Graphics, etc.
(6) Good Unix/Linux or script programming skills.
(7) Good English verbal and written communication skills and willingness to work within a global team.
(8) Good learning competency, self-motivation, and be able to work on diverse areas in a flexible environment.
Please send your resume to : caohtao@cn.ibm.com
Welcome to write to ask Job related information.
Job Scopes & Responsibilities:
IBM Layout Design Engineers are working on cutting-edge Digital Custom and Mixed-Signal Circuit IP layout design (e.g. High-Speed Interface, Memory Array, PLL, High-Speed SerDes,Advanced Processor, etc...) on SOI 45nm, 32nm, and beyond semiconductor technologies for IBM ASIC and Foundry clients. The candidates will be closely working with worldwide design
teams and responsible for/participate in:
(1) Perform layout design which includes low level IP blocks as well as IP layout integration which minimizes area, provides high reliability, DRC/LVS clean, and meets all committed schedules.
(2) Develop initial floorplan and power/ground distribution.
(3) Interact closely with circuit designers to assure all design 0bjectives are being met.
(4) Deliver on schedule, all physical design rules which pass DRC/LVS.
(5) Perform yield and reliability assessment of the physical design.
Job Requirements:
(1) EE or related background in digital/analog circuit design areas.
(2) Industry experience (1-2 years as entry level, more is preferable) in related areas.
(3) Solid knowledge in deep submicron or nanometer CMOS device, process and technology.
(4) Solid knowledge and understanding of DRC/LVS and extraction procedures.
(5) Solid knowledge in relevant EDA tools and environment, such as Cadence, Synopsys and Mentor Graphics, etc.
(6) Good Unix/Linux or script programming skills.
(7) Good English verbal and written communication skills and willingness to work within a global team.
(8) Good learning competency, self-motivation, and be able to work on diverse areas in a flexible environment.
Please send your resume to : caohtao@cn.ibm.com
Welcome to write to ask Job related information.