做16bit精度,100K速度的ADC
re,而且16位的DSM ADC精度要求也不高,大概3~4 Order single stage的SC-DSM就可以了,在这个精度上MASH结构对stage间Match要求比较高,不太容易。
SAR倒是可以做到16位,但是相对DSM要付出更多努力 。。。。。。
你这个需求的话2nd order SC boser-Wooley结构基本可以达到,有低功耗要求么,其他指标呢
功耗越低越好,兼顾更低频率
100K 算啥水平?对16bit?
If you increase your SDM's order, you pay the price for the more OTAs(thus more current) . At the same time, you can use smaller Over Sampling Ratio(OSR)to achieve your Spec, thus decrease the BW requirement of the OTA(more settling time to spend). There's THE tradeoff. Rule of Thumb calculation:
16bit=6.02*16=96dB, you need 2^7*100KHz=12.8MHz sampling freq(2nd order SDM)
2^6*100KHz=6.4MHz Sampling freq(3rd order SDM or MESH 2-1)
What is your process? Could you please attach more detailed specifications ? Info is not enough to help you out.(
Of course you have to take the decimation filter's consumption into account)
这个指标有点尴尬,音频和一些低频应用的频率都比这个低不少;射频的话很少需要这个精度
RRU中我们用的是15位的,不过这个速度确实有点尴尬
恩,这个也没定,老板在拍脑袋,估计看我下半年没事干
什么结构的SAR可以这个速率可以做到16bit呢?
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