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Mentor与Cadence联手推出OVM

时间:12-11 整理:3721RD 点击:
Since the announcement of the OVM in August, the response has been tremendously positive to the idea of Mentor Graphics and Cadence Design Systems collaborating on the development of a SystemVerilog verification methodology. Our customers and partners have told us that multi-vendor support from the outset makes the OVM the de facto standard for the industry because they no longer have to write different code for every simulator.
In fact, providing such cross-platform compatibility was one of the prime motivations for the project. But it was also obvious that having multiple vendors support the OVM was only one consideration: it also had to provide the functionality required by advanced verification teams.
This joint development effort builds upon the success of Mentor's Advanced Verification Methodology (AVM), which provides the TLM-based infrastructure for building modular, reusable verification components that communicate through well-defined transaction-level interfaces. It also provides a library of base classes to allow users to create constrained-random stimulus, collect and analyze functional coverage information, and include assertions as first-class members of the testbench environment. With successful deployment of the AVM at a number of customers, Mentor has continued to develop new components and capabilities in the AVM. These new features will be part of OVM.
Mentor and Cadence have collaboratively integrated, and jointly evolved the existing methodologies from both companies into a common open verification methodology. The resulting OVM provides additional functionality than what is currently found in AVM3.0, but in a completely backward-compatible way. The underlying infrastructure of TLM communication between components and throughout the hierarchy means that time spent learning and developing verification IP and testbenches with AVM3.0 is also time learning the OVM. Once you've mastered the AVM3.0 infrastructure, you'll easily be able to take advantage of the evolved functionality of the OVM including sequential stimulus and enhanced configurability for verification components and environments and more
Finally, the OVM, will follow the precedent set by Mentor, and now expected by the industry, in terms of releasing the OVM. It has been agreed by both Mentor and Cadence that the OVM will be provided in an open source format under the terms of the Apache 2.0 license agreement upon it's official release.
Please contact us if you have any questions.
For more information about the Mentor's Functional Verification products please visit the Functional Verification page

联手对抗s家的VMM?
提供source code倒是挺有诱惑力的,VMM貌似只提供头文件

对于小公司来说成本太大了.
而且以后S/C/M公司风声一变,以前的积累就废掉一大半.
看看原来的VB程序员有多惨

那就直接用SystemVerilog,C++的程序员应该
不会太惨吧!

sounds great
synopsys' vm make me crazy these days.

so, how u deal with it? throw it away or just bear it?
i think u had few choice when u only had vcs

怎么让你发狂了?自己开发base class基本类库也是一个选择

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