请教task为什么时间没有变化?
时间:12-11
整理:3721RD
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请教一下:
在调用另外一个模块的posedge_task的task set_simple_out的时候,总是少了一个时钟
而且打印的时间为
start time--->time= 5
pos=0 time=5
pos=1 time=5
不知道这个是什么原因?
但是调用top_tb_posedge里面的task my_set则没有这个问题。
module top_tb_posedge;
reg clk;
wire val;
wire [7:0]dout;
wire last_one;
reg val_new;
reg dout_new;
task my_set;
input [3:0] ll;
integer mm;
begin
for(mm=0;mm<4;mm = mm +1)
begin
val_new=1'b1;
dout_new=1'b1;
$display(" my_sime %t at [%d] ",$time,mm);
@(posedge clk);
end
$display(" my_sime %t ",$time);
val_new =1'b0;
@(posedge clk);
end
endtask
//reg [7:0]dout;
//reg val;
//reg last_one;
posedge_task pt
(.clk(clk),
.dout(dout),
.val(val),
.last_one(last_one)
);
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
$display(" before start time--->time= %t\n",$time);
@(posedge clk);
$display(" start time--->time= %t",$time);
pt.data_buffer[0]=1;
pt.data_buffer[1]=2;
pt.data_buffer[2]=3;
pt.data_buffer[3]=4;
//my_set(4);
pt.set_dout_simple(4);
#1000;
$finish;
end
always @(last_one or dout or val)
begin
$display( " last_one=%d,dout=%d,val=%d,time=%t\n",last_one,dout,val,$time);
end
endmodule
//////////////////////////////////////////////////////////////////
module posedge_task(clk,dout,val,last_one);
input clk;
output val;
output [7:0]dout;
output last_one;
reg [7:0]dout;
reg val;
reg last_one;
reg data_buffer[0:255];
task set_dout_simple;
input [3:0]element_num;
integer pos;
reg quit_now;
begin
for(pos=0;pos<4;pos=pos+1)
begin
$display(" ---> simple : pos=%d,time=%d \n",pos,$time) ;
dout=pos;
val=1;
@(posedge clk);
//pos=0;
end
val=0;
@(posedge clk);
end
endtask
task set_dout;
input [3:0]element_num;
integer pos;
reg quit_now;
begin
pos=0;
$display(" --->pos=%d,time=%d \n",pos,$time);
dout=data_buffer[pos];
pos=pos+1;
val=1'b1;
if(element_num<=1)
last_one=1'b1;
else
last_one=1'b0;
quit_now=1'b0;
while(quit_now==0)
begin //{
@(posedge clk);
if(last_one)
begin
val=1'b0;
quit_now=1'b1;
end
else
begin
val=1'b1;
$display(" --->pos=%d,time=%d \n",pos,$time);
dout=data_buffer[pos];
pos=pos+1;
if(element_num==1)
last_one=1;
element_num=element_num-1;
end
end//}
end
endtask
endmodule
在调用另外一个模块的posedge_task的task set_simple_out的时候,总是少了一个时钟
而且打印的时间为
start time--->time= 5
pos=0 time=5
pos=1 time=5
不知道这个是什么原因?
但是调用top_tb_posedge里面的task my_set则没有这个问题。
module top_tb_posedge;
reg clk;
wire val;
wire [7:0]dout;
wire last_one;
reg val_new;
reg dout_new;
task my_set;
input [3:0] ll;
integer mm;
begin
for(mm=0;mm<4;mm = mm +1)
begin
val_new=1'b1;
dout_new=1'b1;
$display(" my_sime %t at [%d] ",$time,mm);
@(posedge clk);
end
$display(" my_sime %t ",$time);
val_new =1'b0;
@(posedge clk);
end
endtask
//reg [7:0]dout;
//reg val;
//reg last_one;
posedge_task pt
(.clk(clk),
.dout(dout),
.val(val),
.last_one(last_one)
);
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
$display(" before start time--->time= %t\n",$time);
@(posedge clk);
$display(" start time--->time= %t",$time);
pt.data_buffer[0]=1;
pt.data_buffer[1]=2;
pt.data_buffer[2]=3;
pt.data_buffer[3]=4;
//my_set(4);
pt.set_dout_simple(4);
#1000;
$finish;
end
always @(last_one or dout or val)
begin
$display( " last_one=%d,dout=%d,val=%d,time=%t\n",last_one,dout,val,$time);
end
endmodule
//////////////////////////////////////////////////////////////////
module posedge_task(clk,dout,val,last_one);
input clk;
output val;
output [7:0]dout;
output last_one;
reg [7:0]dout;
reg val;
reg last_one;
reg data_buffer[0:255];
task set_dout_simple;
input [3:0]element_num;
integer pos;
reg quit_now;
begin
for(pos=0;pos<4;pos=pos+1)
begin
$display(" ---> simple : pos=%d,time=%d \n",pos,$time) ;
dout=pos;
val=1;
@(posedge clk);
//pos=0;
end
val=0;
@(posedge clk);
end
endtask
task set_dout;
input [3:0]element_num;
integer pos;
reg quit_now;
begin
pos=0;
$display(" --->pos=%d,time=%d \n",pos,$time);
dout=data_buffer[pos];
pos=pos+1;
val=1'b1;
if(element_num<=1)
last_one=1'b1;
else
last_one=1'b0;
quit_now=1'b0;
while(quit_now==0)
begin //{
@(posedge clk);
if(last_one)
begin
val=1'b0;
quit_now=1'b1;
end
else
begin
val=1'b1;
$display(" --->pos=%d,time=%d \n",pos,$time);
dout=data_buffer[pos];
pos=pos+1;
if(element_num==1)
last_one=1;
element_num=element_num-1;
end
end//}
end
endtask
endmodule