求大神来一个延时程序
时间:10-02
整理:3721RD
点击:
outd<="00100000";
outd<="00011000";
outd<="00100000";
outd<="00000000";
outd<="00001111";
outd<="01011101";
outd<="11110000";
需要在outd中间加个延时20us的程序,谢了。
outd<="00011000";
outd<="00100000";
outd<="00000000";
outd<="00001111";
outd<="01011101";
outd<="11110000";
需要在outd中间加个延时20us的程序,谢了。
设计一个计数器,对特定频率的时钟进行计数,到指定时间就输出一个结果就行了。
比如,counter对1MHz时钟计数,则用如下Verilog代码产生输出:
if(counter < 20)
dout <= "00100000";
else if(counter < 40)
outd <= "00011000";
else if(counter < 60)
outd <= "00100000";
else if(counter < 80)
outd <= "00000000";
……
……