MSL2164:16串LED驱动器设计指南详解(独家)
Thefour different modes and register definitions are illustratedin the figure below, showing the current waveforms. Thedelay for string 0 is held at 0, and the PWM width is thesame for both strings and all the modes. Datan in thefigure refers to both the dimming data and the phase delaydata presented for the nth frame. For "forward" modePHDLYn specifies the number of processed GSC cyclesafter the processed PHI edge that the string "on" timebegins and the PWMn register specifies the "on" time.
In this mode the falling edge varies with the "on" timewidth programmed in the PWMn register, with the risingedge held constant. In "center" mode, the delay is setfrom the processed PHI edge to the center of the PWM onpulse with width set by the PWMn register. Both the risingand falling edge vary based on the PWMn with the centerheld constant within a processed GSC cycle. In "reverse"mode, the PHDLYn sets the delay from the next frame’sprocessed PHI edge to the falling edge of the PWM "on"time and the PWMn register determines the PWM "on"time. Therefore the rising edge varies with PWMn and thefalling edge is held constant. In "inverse" mode, the delayis set from the next frames PHI edge backwards to thefalling edge of the "on" time. The rising edge varies withthe PWMn register, while the falling edge is held constant.
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