一种基于通用型PCI接口的VHDL-CPLD设计

e.std_logic_unsigned.ALL;

ENTTTY cPCI IS

PORT(clk,rst,frame,irdy:IN STD_LOGIC;

ad_high : IN STD_LOGIC_VECTOR(31 downto 24);

ad_low : IN STD_LOGIC_VECTOR(12 downto 0);

c_be : IN STD_LOGIC_VECTOR(3 downto 0);

trdy,devsel:OUT STD_LOGIC;

cs, r_w :OUT STD-LOGIC;

addr: OUT STD_LOGIC_VECTOR(12 downto 0);

END cpci;

ARCHITECTURE behave OF cPCI IS

SIGNAL addr_map : STD_LOGIC_VECTOR(12 downto 0);

SIGNAL read,write,cs-map:STD_LOGIC;

TYPE state_type IS(s0,s1,s2,s3,s4,s5);

SIGNAL state: state_type;

BEGIN

Identify: PROCESS(clk)- -读、写、从设备的识别

BEGIN

IF rising_edge(clk)THEN

IF c_be=X"6"AND ad_high=X"50"AND state="s1"

HTEN read <= i0 i; - -读

write <= i1 i;

cs_map <= i0 i;

ELSIF c_be=X"7"AND ad_high= X"50"

AND state="s1" THEN

read <= i1 i; - -写

write <= i0 i;

cs_map <= i0 i;

ELSIF state="s0" THEN

read <= i1 i;

write <= i1 i;

cs_map <= i1 i;

END IF;

END IF;

END PROCESS;

Addr_count:PROCESS (clk) - -操作地址的获取与地址的递增

BEGIN

IF falling_edge(clk)THEN

IF state="s1" THEN addr_map< =ad-low;

ELSIF state="s3" THEN addr_map< =addr-map+1;

END IF;

END IF;

END PROCESS;

- - 操作信号的产生

addr <= addr-map WHEN state="s3" or state="s4"

ELSE "ZZZZZZZZZZZZZ"

trdy <= i0 i WHEN state="s3" or state="s4" or state="s5"

ELSE i1 i;

devsel <= i0 iWHEN state="s3" or state="s4" or state="s5"

ELSE i1 i;

cs <= i0 iWHEN state="s3" or state="s4" ELSE i1 i;

r-w <=NOT clk WHEN write= i0 iAND (state=s3 or state="s4")ELSE i1 i;

state-change:PROCESS(clk,rst) - - 状态机的变化

BEGIN

IF rst= i0 iTHEN state <= s0;

ELSIF falling-edge(clk)THEN

CASE state IS

WHEN s0 = >

IF frame= i1 iAND irdy= i1 iTHEN state <= s0;

ELSIF frame= i0 i AND irdy= i1 i THEN state <= s1;

END IF;

WHEN s1 = >

IF cs_map= i1 iOR (read= i1 iAND write = i1 i)

THEN state <= s0;

ELSIF irdy= i1 iAND read= i0 i THEN state <=s2;

ELSIF frame= i0 iAND irdy= i0 iAND write= i0 i

THEN state <= s3;

ELSIF frame= i1 iAND irdy= i0 iAND write= i0 i

THEN state <= s4;

END IF;

WHEN s2 = >

IF frame= i1 iAND irdy= i1 iTHEN state <= s0;

ELSIF frame= i0 iAND irdy= i0 iAND read= i0 i

THEN state <= s3;

ELSIF frame= i1 iAND irdy= i0 iAND read= i0 i

THEN state <= s4;

END IF;

WHEN s3 = >

IF frame= i1 iAND irdy= i1 iTHEN state <= s0;

ELSIF frame= i0 i AND irdy= i1 i THEN state <= s5;

ELSIF frame= i1 iAND irdy= i0 i THEN state <=s4;

ELSIF frame= i0 i AND irdy= i1 i THEN state <= s3;

END IF;

WHEN s4 = >

ELSIF frame= i1 iAND irdy= i0 iTHEN state <= s4;

END IF;

WHEN s5 = >

IF frame= i1 iAND irdy= i1 iTHEN state <= s0;

ELSIF frame= i0 i AND irdy= i0 iTHEN state <= s3;

ELSIF frame= i1 iAND irdy= i0 i THEN state <=s4;

ELSE state <= s5;

END IF;

WHEN OTHERS = >state <= s0;

END CASE;

END IF;

END PROCESS state_change;

END behave。

5 MaxPlusII的验证

设计CPLD时，可使用MaxPlusII软件来进行逻辑综合、功能模拟与定时分析。本例选用 Altera 的Max7000系列在系统可编程器件EPM7064SLC84-5。图5所示是其读写访问的仿真波形图。