cpld fpga 区别

mealy＆moore状态机典型程序

Verilog

// Example of a 5-state Mealy FSM

module mealy (data_in, data_out, reset, clock);

output data_out;

input [1:0] data_in;

input reset, clock;

reg data_out;

reg [2:0] pres_state, next_state;

parameter st0=3'd0, st1=3'd1, st2=3'd2, st3=3'd3, st4=3'd4;

// FSM register

always @ (posedge clock or negedge reset)

begin: statereg

if(!reset)// asynchronous reset

pres_state = st0;

else

pres_state = next_state;

end // statereg

// FSM combinational block

always @(pres_state or data_in)

begin: fsm

case (pres_state)

st0: case(data_in)

2'b00: next_state=st0;

2'b01: next_state=st4;

2'b10: next_state=st1;

2'b11: next_state=st2;

endcase

st1: case(data_in)

2'b00: next_state=st0;

2'b10: next_state=st2;

default: next_state=st1;

endcase

st2: case(data_in)

2'b0x: next_state=st1;

2'b1x: next_state=st3;

endcase

st3: case(data_in)

2'bx1: next_state=st4;

default: next_state=st3;

endcase

st4: case(data_in)

2'b11: next_state=st4;

default: next_state=st0;

endcase

default: next_state=st0;

endcase

end // fsm

// Mealy output definition using pres_state w/ data_in

always @(data_in or pres_state)

begin: outputs

case(pres_state)

st0: case(data_in)

2'b00: data_out=1'b0;

default: data_out=1'b1;

endcase

st1: data_out=1'b0;

st2: case(data_in)

2'b0x: data_out=1'b0;

default: data_out=1'b1;

endcase

st3: data_out=1'b1;

st4: case(data_in)

2'b1x: data_out=1'b1;

default: data_out=1'b0;

endcase

default: data_out=1'b0;

endcase

end // outputs

endmodule

Verilog

// Example of a 5-state Moore FSM

module moore (data_in, data_out, reset, clock);

output data_out;

input [1:0] data_in;

input reset, clock;

reg data_out;

reg [2:0] pres_state, next_state;

parameter st0=3'd0, st1=3'd1, st2=3'd2, st3=3'd3, st4=3'd4;

//FSM register

always @(posedge clock or negedge reset)

begin: statereg

if(!reset)

pres_state = st0;

else

pres_state = next_state;

end // statereg

// FSM combinational block

always @(pres_state or data_in)

begin: fsm

case (pres_state)

st0: case(data_in)

2'b00: next_state=st0;

2'b01: next_state=st4;

2'b10: next_state=st1;

2'b11: next_state=st2;

endcase

st1: case(data_in)

2'b00: next_state=st0;

2'b10: next_state=st2;

default: next_state=st1;

endcase

st2: case(data_in)

2'b0x: next_state=st1;

2'b1x: next_state=st3;

endcase

st3: case(data_in)

2'bx1: next_state=st4;

default: next_state=st3;

endcase

st4: case(data_in)

2'b11: next_state=st4;

default: next_state=st0;

endcase

default: next_state=st0;

endcase

end // fsm

// Moore output definition using pres_state only

always @(pres_state)

begin: outputs

case(pres_state)

st0: data_out=1'b1;

st1: data_out=1'b0;

st2: data_out=1'b1;

st3: data_out=1'b0;

st4: data_out=1'b1;

default: data_out=1'b0;

endcase

end // outputs

endmodule // Moore

使用状态机做时钟产生电路－独特却又最为精准（ＣＰＵ设计中常用方法）

介绍一款时钟发生器－－独特却又最为精准（ＣＰＵ设计中常用方法）
时钟发生器 clkgen 利用外来时钟信号clk 来生成一系列时钟信号clk1、fetch、alu_clk 送往CPU的其他部件。其中fetch是外来时钟 clk 的八分频信号。利用fetch的上升沿来触发CPU控制器开始执行一条指令，同时fetch信号还将控制地址多路器输出指令地址和数据地址。clk1信号用作指令寄存器、累加器、状态控制器的时钟信号。alu_clk 则用于触发算术逻辑运算单元。
module clk_gen (clk,reset,clk1,clk2,clk4,fetch,alu_clk);
input clk,reset;
output clk1,clk2,clk4,fetch,alu_clk;
wire clk,reset;
reg clk2,clk4,fetch,alu_clk;
reg[7:0] state;
parameter S1 = 8'b00000001,
S2 = 8'b00000010,
S3 = 8'b00000100,
S4 = 8'b00001000,
S5 = 8'b00010000,
S6 = 8'b00100000,
S7 = 8'b01000000,
S8 = 8'b10000000,
idle = 8'b00000000;

assign clk1 = ~clk;

always @(negedge clk)
if(reset)
begin
clk2 = 0;
clk4 = 1;
fetch = 0;
alu_clk = 0;
state = idle;
end
else
begin
case(state)
S1:
begin
clk2 = ~clk2;
alu_clk = ~alu_clk;
state = S2;
end
S2:
begin
clk2 = ~clk2;
clk4 = ~clk4;
alu_clk = ~alu_clk;
state = S3;
end
S3:
begin
clk2 = ~clk2;
state = S4;
end
S4:
begin
clk2 = ~clk2;
clk4 = ~clk4;
fetch = ~fetch;
state = S5;
end
S5:
begin
clk2 = ~clk2;
state = S6;
end
S6:
begin
clk2 = ~clk2;
clk4 = ~clk4;
state = S7;
end
S7:
begin
clk2 = ~clk2;
state = S8;
end
S8:
begin
clk2 = ~clk2;
clk4 = ~clk4;
fetch = ~fetch;
state = S1;
end
idle: state = S1;
default: state = idle;
endcase
end
endmodule
//--------------------------------------------------------------------------------

由于在时钟发生器的设计中采用了同步状态机的设计方法，不但使clk_gen模块的源程序可以被各种综合器综合，也使得由其生成的clk1、clk2、clk4、fetch、alu_clk 在跳变时间同步性能上有明显的提高，为整个系统的性能提高打下了良好的基础。
诸位．这样的时钟发生器无论在时序上还是功能上都是完美的，难怪一直在ＣＰＵ设计中采用．