深入分析verilog阻塞和非阻塞赋值

原文链接：学verilog 一个月了，在开发板上面写了很多代码，但是始终对一些问题理解的不够透彻，这里我们来写几个例子仿真出阻塞和非阻塞的区别，我们先上代码module LED  (    CLK, RSTn,    scan,    flag ,    c,    ,one,two,three,four);     input CLK;     input RSTn;     input scan;     output flag,c;     output [3:0] one,two,three,four;/***********************************************************/        reg F1,F2;    reg a,b;    reg [3:0] one,two,three,four; /********************信号传递之间的非阻塞赋值***************************************/    always @ ( posedge CLK or negedge RSTn )   //      if( !RSTn )         begin           F1 <= 1&#39;b1;           F2 <= 1&#39;b1;      end      else  begin   F1 <= scan;   F2 <= F1;      end /*******************信号传递之间的阻塞赋值****************************************/    always @ ( posedge CLK or negedge RSTn )   //      if( !RSTn )         begin           a = 1&#39;b1;           b = 1&#39;b1;      end      else  begin   a = scan;   b = a;      end /******************数据加  非阻塞赋值  先判断后计数*****************************************/      always @ ( posedge CLK or negedge RSTn )   //one <=  if( !RSTn )   begin    one<=0;   end  else  begin   if(one==14)       one<=0;   else          one<=one+1;  end/***************数据加  非阻塞赋值  先计数后判断********************************************/    always @ ( posedge CLK or negedge RSTn )    //  two<=  if( !RSTn )   begin    two<=0;   end  else  begin   two<=two+1;   if(two==14)    two<=0;  end /**************数据加  阻塞赋值  先判断后计数*********************************************/ always @ ( posedge CLK or negedge RSTn )  //three =  if( !RSTn )   begin    three=0;   end  else  begin   if(three==14)    three=0;   else    three=three+1;  end/*************数据加  阻塞赋值  先计数后判断**********************************************/ always @ ( posedge CLK or negedge RSTn )  //four =  if( !RSTn )   begin    four=0;   end  else  begin   four=four+1;   if(four==14)    four=0;  end            /****************信号之间传递***********************/ assign flag = F2 & !F1;assign c  = b  & !a;/***************************************/ endmodule      2、我使用modesim 仿真，下面为我的  test bench `TImescale 1 ps/ 1 psmodule LED_vlg_tst();// constants                                          // general purpose registersreg eachvec;// test vector input registersreg CLK;reg RSTn;reg scan;// wires                                              wire c;wire flag;wire [3:0]  four;wire [3:0]  one;wire [3:0]  three;wire [3:0]  two;// assign statements (if any)                         LED i1 (// port map - connecTIon between master ports and signals/registers   .CLK(CLK), .RSTn(RSTn), .c(c), .flag(flag), .four(four), .one(one), .scan(scan), .three(three), .two(two));/*iniTIal                                               begin                                                 // code that executes only once                       // insert code here --> begin                                                                               // --> end                                            $display("Running testbench");                      end                                                   always                                                // opTIonal sensitivity list                          // @(event1 or event2 or .... eventn)