ARM Cortex-A53处理器详细介绍

No

Yes

Efficient 64-bit immediate generation

Less need for literal pools

No

Yes

Large PC-relative addressing range

(+/-4GB) for efficient data addressing within shared libraries and position-independent executables

No

Yes

Tagged Pointers

Useful for dynamically typed languages such as Javascript, and for garbage collection

No

Yes

64k pages

Reduce TLB miss rates and depth of page walks

No

Yes

New exception model

Reduces OS and Hypervisor software complexity

No

Yes

Enhanced Cache management

User space cache operations improve dynamic code generation efficiency, Data Cache Zero for fast clear

No

Yes

Cortex-A53 Architectural Features

Feature

Benefits

In-Order Pipeline

Lower power consumption. Performance improvements are sought elsewhere in the design, e.g. the memory system and issue capability.

Increased dual-issue capability

Increased peak instruction throughput via duplication of execution resources, and dual instruction decoders.

Power optimized L2 cache

Efficiency optimized L2 cache design delivers lower latency and balances performance with efficiency.

512 entry main TLB

Improved performance on code with complex memory access patterns, e.g. web browsing. Larger main TLB than Cortex-A7 and Cortex-A9.

Small, fast uTLBs

10 entry uTLB with an extremely short miss penalty to reload from the main TLB allows excellent performance in a small area and power footprint.

Advanced Branch Predictor

4Kbit Conditional Predictor, 256 entry indirect predictor increase branch hit rate.

64B cache lines

Fully aligned with Cortex-A57 microarchitecture to simplify cache management software in big.LITTLE systems. 64B line sizes a good tradeoff for modern memory access patterns.

Non-blocking I-fetch with multi-line pre-fetch

Increased instruction throughput across more types of benchmarks, from control code to processing intensive loops.

Dual identical ALU pipelines

Increased opportunity to dual-issue instructions, at a small additional area.

64b store path

Balances store bandwidth with dynamic power consumption, focused on a highly efficient design tradeoff.

Multi-stream pre-fetcher

Greater data flow into the main datapath increases overall performance on a wide range of code.

Increased D-side throughput

3-outstanding load miss capability (per-core, excluding prefetches); 8-outstanding transactions (per-core)

Extensive power-saving features

Heirarchical clock gating, power domains, advanced retention modes.

Cortex-A53 Advanced Multicore Features

The processor also utilizes the widely established ARM MPCore multicore technolo