lmx2326
1-do you have the correct charge pump polarity programmed into the IC? You can set it so that Kv is positive or negative, to compensate for Tuning polarity changes in the VCO
2-use the National Codeloader program, can you program the Fo/LD pin to output the divider outputs? That way you can see that your Reference and RF paths are working
3-What reference frequency are you using?
4-What PCB did you use? If you built it yourself, are you sure the layout is correct? How about soldering the part down?
5-How are you supplying voltage to the Circuit?
Dave
www.keystoneradio.com
1. I'am using +ve polarity to program the chip as the VCO needs +ve tuning voltage(0V to +5V) for tuning. I hope this is correct? (As a trial i tried changing this to -ve also but as would be expected, it did not help)
2. I'll try to do this today. thanks for this suggestion
3.Reference frequency is 10MHz (clipped sinewave, peak to peak voltage ~4V), being generated from a XO.
4. I have got this PCB designed by a professional PCB designer and hope it is laidout corretly. I have verified various sections and did not find any this wrong. The components are also soldered correctly.
5. The supply to the circuit is through a precision power supply (Agilent E3620A). I have verified at the VCC pins of all the components and found the voltages reaching correctly (+4.7V)
-Have you ever checked the carrier at SA so that the PLL "really" tries to pull down the frequency of the VCO to the programmed value?
-Observe charge pump pulses at the output of the PLL IC before entering loop filter ..You'll probably see very small duty cycledthin pulses..
-Input level which is fedbacked from VCO can be too much or too low for the PLL
....
theremight be many reasons that can create this issue..
-I am checking the carrier on a spectrum analyzer and it always remains at the frequency corresponding to vt=0v (~1649 MHz). never noticed if there was momentary action of pulling up or down to programmed value.
-will try checking the charge pump pulses.thanks
-i have checked the vco feedback power going to the pll chip it is around -2 to -4 dBm (pll sensivity range is 0 to -10 dbm)
-Can the TCXO power also be the cause of trouble. the peak to peak voltage in the tcxo signal feeding the pll is ~3.8V. Is this too much?
Have you checked any bit reversal while loading the register. Select a frequency which is having non zero control voltage. you need to check at with voltage at charge pump
Today while working with my 2326 based PLL I noticed two spurious peaks 10MHz away from the VCO oscillation frequency (corresponding to vt=0volts) on either side of the main carrier. I feel that the reference signal (10MHz) is modulating the VCO signal and producing these sidebands. Is this normal or should be avoided.
The other thing that I noticed was that the reference signal was seemingly distorted (square wave with lot of overshoots)
Could these be reasons for the PLL not getting locked.
I am not getting any useful signal at the FO/LD pin when I tried to prgram it to outout the value of R divide or N counter. Why?
it is normal
Put low value capacitor to minimize the overshoot.
find the ways using debug instructions like you can get the output of R divider output and other stuff like that
If you are using a 10 MHz reference at the phase detector, then you should expect some sidebands at +/- 10 MHz from the VCO carrier. This is because there is an small pulse coming outof the phase detector at a 10 MHz rate, and a small portion of that gets to the VCO tune line. You can try to lowpass or notch filter it out, but have to be careful to not lose any phase margin in the control loop.
IF you divide the reference clock down to some lower frequency before it hits the phase detector, then you would expect the sidebands at +/- that lower frequency.
As far as locking, I gave some bench test ideas for debugging in this thread:
https://www.edaboard.com/ftopic334538.html