measuring phase noise

Im using the ad4252 dual pll eval board. I populated the board with my vco's and loop filters. I connected my spec analyzer to the RF port of the eval board and manipulated the channels with analog devices software. I attached a screenshot of the VCO RF ouot frequency at 2238MHz. Well now that I obtained the vco frequency on the spectrum analyzer How do I measure the phase noise with my spectrum analyzer?

To do the Phase Noise you need to have the VCO sending out a CW tone(Locked).
Then with your spec An there might be (Under "Measurements") a Phase Noise
profile. Just get the manual and follow the instructions. If you don't have that
Read this link:

http://www.national.com/an/AN/AN-885.pdf#page=1

Cheers

Seems to me that the PLL loop is not locked. If locked you should see a pure sinewave carrier. For measuring phase noise:
* Use the phase noise module if the spectrum analyzer has one
* Use noise measurement at 10/100 kHz offset with the VCO locked

This PLL is not locked...

Use the following formula to calculate the Phase Noise using the Spectrum Analyzer:

PN_on_SA[dBc/Hz] = Carrier_Power[dBm] ? Noise_Power[dBm] ? 10*LOG(RBW[Hz])

where:
- Carrier Power is the power of your signal measured on the SA display.
- Noise Power is the power of the noise at a specific frequency offset.
- RBW is the Resolution Bandwidth of your SA during measurement.

I'd have to agree, this PLL is either not locked or the reference signal is very noisy.

This is a common problem--you design a PLL and it does not work. The solution can be fairly complex, though, as any number of things may be going wrong. Here are a few ideas about how to get started:

* You know what frequency it should be at (you programmed the divisors and know the reference frequency). What is the corresponding VCO tune voltage that goes with that one frequency? Say it is +2.5 Volts. Hook up a voltmeter to the tune line and see what the voltage is. If it is near 0 volts or near 5 volts, obviously it is not even locked. Check to see if the chip is programmed right, if the correct pwer supply voltages are present to drive the chip and VCO. Try programming the chip with a wide range of different divisors, and see if any of them lock up (some divisors are illegal in some chips).

* If the voltage is approximately the right tuning voltage, then MAYBE it is locked (or trying to lock). Change the reference frequency slightly up or down (i.e. replace the reference clock with a tunable synthesizer). Does the VCO track up and down too? If so, you either have a high noise source (reference clock is not good enough, voltage regulator is oscillating, op amp is oscillating, etc), OR you have an unstable loop. Try other loop parameters for the loop filter, typically narrower bandwidth. If you can see a very distinct sine wave (in the 10 KHz to 5 MHz range) on an oscilloscope hooked up to the VCO tune line, that is a pretty good indication that the loop is unstable and oscillating.

* If you can get the thing to lock up with any of the above, do the math to figure out if it is at the right frequency. If you are dividing the VCO by 1000, and dividing the clock by 10, then your VCO should be 100.00000 times the clock frequency. If it is 100.013, then it is misprogrammed. It is easy to get the divisor ratios off by one bit.

* After you have the thing at least locked up and tracking the clock at the right frequency, then you can play around trying to get things better. You can try a lab standard crystal oscillator in place of the clock you are using to see if the noise gets better. You can try different phase detector frequencies and divisior ratios, and different loop bandwidths, trying to get it to have better phase noise.

* One trick to measure stability would be to inject a known disturbance, and see how the loop reacts to it. AC coulple in a square wave of say 50 mV onto the VCO tune line. Hook an oscilloscope probe to the tune line and see how the loop responds to this step disturbance. You want to see a step in voltage, followed by an exponential ramp back to the correct VCO tune voltage, with little or no overshoot. If it rings for many cycles, you have a marginally stable loop--fix your loop filter accordingly.

Well I found one stupid mistake. My R value was not set properly in the software. It was set to 1 but should have been set to 10. My reference frequency is 10MHz and my step size is 1MHz. I think it is something wrong with programming of the PLL chip. My vco output is 2038MHz which equates to 0 volts. So I know the VCO is working...the quest continues....