PLL problem [hlp]
I have used ADIsimPLL software to design a PLL. But the designed schematic seems to be wrong. You can see part of the schematic in the attached image. The software inserts two MUXOUT pin (pin 14) for the PLL. Which of them must be used?
It seems that there is a mistake in the software.
It is pin 1 (see EVAL-ADF4156)
Why not ask directly to AD support?
I hope it can help.
Mazz
You should study the data sheet more carefully. Obviously the MUX out can have two uses, depending on how you program the chip. In the upper part of your schematic, the mux out is operating like a switch to ground--when open the loop bandwidth is narrower, and when short circuited the loop bandwidth is (temporarily) wider which will allow for faster lockup.
In the bottom, the MUX is programmed differently--as a lock detector.
You choose which of the two circuits you want to use, and ignore the 2nd circuit.
by the way u can see the patents which they contain many practical circuits
Hello;
biff44 wrote:
If I want to use MUXOUT as Lock Detect output, how the schematic of loop filter should be changed?
just like biff44 had said, you ignore the top mux portion which means you remove r1, r1a and c2
In AD eval board schematic it is shown that the correct pin to use is pin 1.
Mazz
Well, you can remove r1 for sure, but if you remove r1a and c2 it will probably start to oscillate. R1a and C2 form a zero which gives you some phase margin in the control loop.