regarding divider
时间：04-09
整理：3721RD
点击：
hi
i want to design a pll for three bands
to get lock to the three differnt bands i have to get the divide ration as 64 to 148
for that i am using the dual modulas counters with prescalar 8/9 program counter as 5 bit counter and swallow counter as 3 bit counter
can any body give the architecture for the above counter especially 5 bit synnchronous counters....
i want to design a pll for three bands
to get lock to the three differnt bands i have to get the divide ration as 64 to 148
for that i am using the dual modulas counters with prescalar 8/9 program counter as 5 bit counter and swallow counter as 3 bit counter
can any body give the architecture for the above counter especially 5 bit synnchronous counters....
There are mang dual modulus divider architecture on IEEE papers,and the counter is not difficult to desig.If your output frequency is not very high ,you can design the couunter by verilog.