What should I notice designing a PA by CMOS technology

Hi, I want to design a PA by CMOS technology. I found that the architectures of PA in the books are easy. Why do so many people say it is difficult to design a PA? What should be noticed when I design a PA by CMOS technology. Thanks!

I am designing PA too now.

Is difficult because CMOS has a low break-down voltage, low efficiency, leakage of the PA circuit through substrate to other circuits on the same die, low accuracy of the models compare to other processes, impedance matching difficult compare to other processes…

low quality factory of inductors

By the way.. which technology are you designing? And what is the Class of operation of the PA?

I'm designing one to, in UMC 0.18um. A Class D PA