load pull simulation

Hello, I'm designing a power amplifier and I tried a Load-Pull-Simulation in Cadence... as it is explained in this application note
http://www.cdnusers.org/community/vi...RF_PA533AN.pdf

My Question: To obtain the optimum load for maximum output power I have to plot the power contours and look for the "X". Unfortunately it was not explained how I have to match the input of my amplifier. And now I discovered that the contours (the related load impedance) are depending on the input matching. - I'm confused because I thought that the input matching influences the power gain but not the maximum output power (1dB-compression point).

Maybe someone can help me?

Infact input matching influences available optimum power because of putput impedance is depended on S11 due to S12..
But it should not influence too much..

The input matching do influence the power contour. However, this effect is limited.
For MOS FETs, input matching has little effect to the power contour. But for bipolar transistor, input matching has a larger effect compared to that using MOS FETs.