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stripline filter

时间:04-08 整理:3721RD 点击:
I designed some filters ( interdigital ) using Serenede 8.7 or Eagleware.
But tested filters have bad return loss , also rejection is not like simulation. Anyone design and test ? Any comments that might help put design right.
frequency was 2-3ghz n=11 rogers4003 60mil 1-0.5oz copper with film to join them toghether.

Via inductance comes into play at these frequencies. Does your design include these effects? Genesys has the simulation capability of including these at two levels, the basic simulator/optimizer and the multidimensional E&M simulator.

[Yes I included 2 via microstrip in parralel.
By the way I PRINTED BOTH sERENEDE AND EAGLEWARE design, all suffered the same problem, bad R.L. -10DB TO -13DB TYPICAL FOR WORST CASE IN BAND.

Why did you build the filters in stripline configuration (two groundplanes) instead of microstrip configuration (single goundplane)? Was it really required to avoid cavity mode propagation, stop band attenuation, etc?

Are you sure you have manufactured the stripline filters using the right Duroid substrate material, i.e. are you sure of the epsilon-r is the same in the simulations as in the material? In addition, what does the stripline look like? The stripline filter layer stack shall consist of:

groundplane
dielectric material (Rogers Duroid)
stripline conductor (etched copper track)
dielectric material (Rogers Duroid)
groundplane

A microstrip filter consists of:

microstrip conductor (etched copper track)
dielectric material (Rogers Duroid)
groundplane

Duroid thickness is important as well. Most stripline filters consist of a dual copper side Duroid substrate and a cover laminate (single copper side). The dual copper side substrate has etched tracks on one side and unbroken copper on the other side. The cover laminate is put ontop the etched filter, having the ground copper plane facing away from the etched filter tracks. Now. it's important the cover laminate is pressed against the filter tracks for maintaining correct dielectric thickness. No vertical air gap is allowed. Pressure is usually applied via two chassis halfes where in between the filter is mounted. When the two chassis halfes is assembled, the stripline filter stack is squeezed together.


What I was getting at is that vias have inductance which the program takes into account in the design. Unless you use the via dimensions that the program assumed, the results will be different. Genesys allows you to specify the via diameter and uses one via.

sTRIPLINE=High stopband rejection and yes I thought that I considered everything, but the Return Loss is not good enough.

Use Ansoft HFSS or Sonnet to get more accurate simulation results. And decrease the height of the substrate to get more stopband rejection.
Circuit simulators (serenade, genesys) use closed-form formulation. They don't show the leaky mode, or higher order modes. I advice you to use EM simulation tools such as HFSS, Sonnet, IE3D, CST and so on.

Could you give me the exact specs of the filter?

regards,
Lkuzu@yahoo.com

It's not easy to help you when you only give us these short explanations...

But we understand n=11 means an 11-pole interdigital stripline filter. At these very high orders, manufacturing tolerances becomes critical. If you run a sensitivity (Monte Carlo) or tolerance analysis in your design program you will realize this. A better way is to split an 11-pole filter into say, one 5-pole and one 6-pole filter, having an isolating amplifier between. Then each filter becomes less critical.

Maybe you can borrow a digital camera and take a couple of close-up photos of your design? Then you can attach the JPEG's her for us to view. Important is to see how you attach the connectors to the filter assembly, the shape of ground via holes, how the chassis looks like and how you maintain correct substrate thickness.


Did you take into account the possibility of variation in adhesive thickness? Also, what exactly are you testing? Are you testing the vertical transitions and the filter or are you deembedding using a TRL cal? If you are not doing a TRL cal, you need to optimize the transition from the stripline to the test cable.

The stripline design in this case was really a diplexer made of 2 interdigital filters, and yes I USED A BONDING FILM to put them toghether. I will prepare a file including both EAGLEWARE and Serenade DXG+ material design.
You (I mean all the participants in this discussion) were CORRECT AND VERY HELPFULL:
a.I did not include in the design the transition to connectors or mounting substrate. I should have integrated them in the design!
b.I approximated the influence of the bonding film.

So I will prepare some zip files of the design, and results, so maybe we can learn something usefull of all that mess.

hi,
U have to do same EM simulation to validate your measured results like ADS mom,sonnet .

Come with your probelm clearly.

With Regards
Viswanathan.B

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