Supply voltage influences Class E power amplifier's eff?

Hi All,

I'm simulating a simple single-ended Class E power amplifier with certain GaN HEMT under 2GHz or higher. Its output power is around 10W.

The strange thing is that the supply voltage (drain bias voltage) can influence the optimum efficiency dramatically...

For example, when the transistor's biased at 28V, OK, I can get 72 or 75% drain efficiecny with load pull method. Howerver, when it's biased at 50V, I can only get 63 or 64% efficiency...

I looked throng some books. They only said the on-resistors*output capacitance can put a limit on the achievable efficiency, but not mentioned supply voltage.

Anyone can help? Any suggestion will be good...

Output capacitance has not a constant value ,instead it's Vds bias dependent( because, Cds is a reverse polarized P-N junction..).
So, when you increase/decrease your Vds, output capacitance will be influenced.
Generally, output capacitance has a value inverse proportional to Vds (or simply Vcc)

Normally, higher Vdd will achieve lower output capacitance, then I should get higher efficiency, not lower...