need help about LDMOS PA design

hi, anyone have example of ldmos PA ? i have question about how to determine the location of bias on the in\out matching lines and design of RF choke for DC.
Why the design in the datasheet use two symetrical decouple path?

That is for higher VBW band.

Which transistor are you using ? I have some experience with Freescale MRF types and may be able to help

I am using freescale MRF. Hope your help