PLL lose lock sometimes when turn on the power
And if the PLL lose lock when turn on the power,it would always in unlock, even I reconfiged it,unless I turn off the power, and then turn on it again.
It is not everytime that the pll is unlock when turn on the power. In most time I turn on the power, it is in lock .
I found that if the PLL is unlock when turn on the power, the current of the PLL is fewer than lock conditions. But the voltage is the same.
My PLL power AVDD and DVDD are all come from LDOs, and are decoulped by 4.7uf,0.1uf,47pf.
Sounds like some sort of power supply sequencing problem. It could be a number of issues. Off the top of my head:
1) microprocessor is sending information before the PLL supply voltage is high enough to receive it. Need to delay when the micro sends data after a power up.
2) PLL has an op amp that is stuck at one of the supply rails. In that condition, it might have low op amp gain, and is unable to respond to phase detector outputs urging it to lock up.
3) Op Amp locks at a negative rail, and the VCO only wants positive tuning voltages to operated correctly (or visa versa), so the VCO stops oscillating, and PLL has no signal to lock to. Need to add a series R and schottkey clamp diode on tune port.
4) Control loop is marginally stable. Need more phase margin to withstand big perturabtions.
Rich
And let's not forget the possibility that the power supply surge causes a glitch in the Latch Enable pin, ruining the chips' programming. Sounds like this is out of the regulators way, too.
You need to probe the LE pin whilst replicating the condition that unlocks your chip. Use single shot, negative edge trigger and set the trigger level to something lower than the logic high level.
One more point:
Check you LDO if it start up normally.
Does your lock range (pull-in range) exceed the tune range of
the VCO? If not, then you could be bumping Vtune beyond
the ability to pull in.
If you have a ring-oscillator style "VCO", are you sure that overtone
operation is impossible? Non-prime-number stage counts are
able to go multimode.
thanks for your reply.
the problem has been solved. I add a Res to ground on the SCLK line.