LNA gate bias with resistor or inductor?
For an X-band MMIC LNA with phemt, can the gate be biased with TFR(thin-film resistor) instead of inductor & microstip, since the TFR can save much die area.
I found the TFR model in the design kit is very different from resistor, E.G. a 20K ohm resistor will be no more than 1K ohm @10GHz. When do circuit simulation with model in ADS, the LNA will work still; but when doing full EM simulation with Momentum, the resistor will lead cuirt failure, even the DC current is not correct.
Gate biasing with resistor will work in LNA lower than 3GHz (I have verified), though,
I am afraid resistor can not be used for gate baising in high frequency such as X band?
Can anybody join to disscuss it? Thanks in advance!
Make the resistor small, to minimize the area -> minimize the parasitic capcitance to the substrate.
Cannot use only resistors for pHEMT gate bias at high frequencies.
Hi,Volker:
You mainly refer to parastic capacitance to substrate?
In the resistor model, it is said that the parasitics become distributed in high frequency.It is suggested to use "thin film resistor" model (such as "TFR" in microstrip palette in ADS simulator), but i think this model is only for straight resistor layout. In many cases, we use winding resistor.
However, I take the winding resistor to do EM simulation, and take the s2p file into the schematic, the LNA also works well. Should I trust this result? or anything else unconsidered?
In the design kit, except NiCr TFR resistor, it also provide another resistor:N+ Epitaxial Resistors, maybe this Epi resitor can reduce the parastic capacitance to substrate?
Hi, Vfone:
Would you pls explain more clearly? why not only resistor? and which kind of biasing is better?
Thanks for everyone!
This was the effect that seems most obvious to me, and might explain the high frequency issue.
On PCB, I have used gate bias network with a combination of SMD resistor and lines up to 24GHz, so I am not aware of a fundametal frequency limit. But maybe I miss something, so I am curious what vfone refers to.
I would trust EM results more than a simple TFR circuit model.
Hi,Volker, thanks
I thought SMD resistor may also has too much parastic capacitance and inductance, only the parastic indutance has no effect. In many cases, lambda/4 high-resistance T-line along with open stub is used for gate biasing. But in X bad, it is impossible to implement it on chip.
Yes, in general you are right. I had selected a resistor series that seemed approriate and measured it on the VNA, so that I could include the parasitics in my design. It was a combination of resistors and the usual lambda/4 lines + radial stub, because a bias networks made of lines only had coupling issues in my specific case (multiple stages). I understand that you are working on-chip and just mentioned my stuff because it was resistors in a bia snetwork at high frequency, in the presence of parasitics.
Because of size? Yes, i can see that.
When I read your initial description, my first idea was that your TFC model might not be accurate. If you have done a careful EM analysis with the proper stack up and things look good there, I would trust the EM results and question the TFC model. Recently, I have worked quite a bit in RFIC passive modelling and yes, I have seen a couple of mistakes in foundry passive models.
Many thanks for volker's warmly disscussion! I will try to do EM simulation in place of TFR model.
Thanks again!