Power amplifier attenuation

Hi edaboard members!

I am currently designing a Class AB Power Amplifier (in 90nm cmos process) operating at 5.8GHz. In my initial design (which consists of transistor, rf inductor choke and dc block capacitor at the output), I obtained a Power gain of 12.26dB. However, when i implemented the input matching network (circuit that matches the 50ohm source resistance to the input impedance of the PA), the Power gain drastically dropped to -6dB.

To have more details, i probed the voltage at each node ((1) input node, (2) after input matching network or transistor gate node, and (3) output or transistor drain node). Transient simulations showed that the voltages at (1) and (2) are okay, meaning, the waves are smooth and not attenuated. However, voltage at (3) showed an attenuated version, thereby confirming the -6dB value I obtained from my pss simulations.

I am now looking for explanations/lectures/literatures/tutorials/books/conference papers/journals/etc that can give me some explanations why this behavior happens so that I can avoid this and make my PA amplify again.

And I really hope that you can help me with this. Any insight, suggestion and help is very much appreciated.

Thank you very much!

Try to use multi pole input matching network, which helps designing the matching network from low to high impedance.

hi vfone,

by multi-pole input matching network, do you mean ladder LC network?

thanks!

Solved! I checked the port arrangement in my spice file and found out that my output and input ports are interchanged. That means I was matching the wrong network.