How to impedance match interstage when transistors work in triode and cutoff mode ?

Here is a circuit of Class E PA (output stage) with Class F as driver stage. Since both transistors in driver and output stage work in cutoff and triode mode, I am wondering how I can decide the L and C values of interstage impedance matching network for the two modes.

I am guessing for the driver stage transistor. Looking into the this transistor, the impedance I can see is only the drain-source resistance, Rds. Looking into the output stage transistor, the impedance only has to do with Cgs and Cgd. Is this right?

However the output transistor works in two modes, then Cgs and Cgd are different in two modes. That means the input impedance of output stage is different in the two modes (triode and cutoff). Also the Ron of the driver transistor is also different in the two modes. So how can I impedance match the output impedance of the driver stage to the input impedance of output stage because of this?

Hi

for reduced conduction angles classes of operations, the conventional concept of impedance matching is meaningles. You do not see the resistances and capacitances from the equivalent circuit of a transistor. Use nonlinear simulations instead to determine the match numerically.

flyhigh

Thanks. Could you give me more details on the nonlinear simulation tools since I am using Cadence? What tool/method should I use in Cadence to find the L and C value in the interstage matching network?

The question also applies to the input impedance matching of the driver stage. I need to match the input of the driver stage to 50 ohms of the source. Should I use nonlinear simulations to get the inductor Lg1 value?

Hi

Unfortunately, I don't have any experience with Cadence, have used nonlinear simulators in ADS, MWO and long time ago in Serenade from Ansoft. All the nonlinear simulators that I have used were harmonic balance simulators. Not sure, but guess that most time domain (Spice based) simulators should work without any problems (some might have problems if negative L and C values have been used in transistor models - the response becomes non-causal).

First of all, it is a must that you have non-linear model of transistor. Then it is just the matter of setting the simulations, varying the component values and viewing the results, as usual. If non-linear optimization is not available you can use manual adjustment of component values to maximize output power/efficiency. Generally, I think that any RF/Microwave part of your circuit should be analyzed using nonlinear tools. The working regimes of the devices are strongly nonlinear.

flyhigh