S-Parameters in a JFET amplifier
时间：04-07
整理：3721RD
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I am simulating a Common Source FET amplifier in ADS, and analyzing S-Parameters, but I have a few questions.
The simulation result shows really bad S11 (close to 0 dB). I wonder if this is ok. I mean, the amp's input impedance is high, so the huge mismatch is causing this behavior.
The idea here is to use this as a voltage amplifier, not a power amplifier, so is it correct to say that the power reflection is not an issue, as long as a voltage appears in the output?
The simulation result shows really bad S11 (close to 0 dB). I wonder if this is ok. I mean, the amp's input impedance is high, so the huge mismatch is causing this behavior.
The idea here is to use this as a voltage amplifier, not a power amplifier, so is it correct to say that the power reflection is not an issue, as long as a voltage appears in the output?
Yes, could be OK if your signal souce, where the gate is connected, doesn't need to be matched to the load.