104MHz reference clock frequency generation

Hi,

How to generate the 104MHz reference clock frequency using the 10MHz external reference clock?

Thanks in advance...!

Offhand, the only way I can think of is to multiply (using PLL) by 260 and divide by 25, or if you've got an FPGA, use an NCO.

what about 104 and 10

What about them? I should have mentioned that in order to implement an NCO you're going to need to raise that 10MHz frequency with a PLL/DLL

@ barry

That means using the PLL or DDS, we can generate the 104MHz reference clock with 10MHz external clock.

Isn't it?

I don't think you can use the PLL to generate the 104 directly since 104 is not an integer multiple of 10. But I'm not an expert on PLLs; maybe there's a way I'm not aware of.

You can generate almost any fractional multiple you like with the right PLL/synthesizer chip. 104MHz from 10MHz should be no problem. There are clock generator chips based on PLLs that may do what you want. It is a while since I looked at them but have a look for the ICS525.

Keith

Keith,

That chip you mention is nothing more than a pll with a divider/multiplier arrangement. You need to have integer mutliplier and divider terms; you can't multiply by 10.4. As I posted originally, I think the smallest terms you can use is a multiplier of 260 and divider of 25. This type of device won't work unless it's got a VCO that can go upt to 2.6GHz.

Of course you can generate 104MHz from 10MHz! If you couldn't, how would you ever get 25kHz channels on a radio with a simple clock reference? The PLL simply divides the incoming frequency down to a suitable reference. There is no need to multiply up to 2.6GHz. You need to check out how frequency synthesizers work. These are the settings from the online ICS525-01 calculator to get 104MHz from 10MHz.

You can also use the -02 version. The calculator can be found at IDT - Integrated Device Technology - Calculators

As I say, it is a while since I have used it and so it is an old chip - there may be better ones around. They are great for doing things like generating pixel clocks for different broadcast standards or other applications where you want a weird clock from a simple clock source.

Keith.

---------- Post added at 18:57 ---------- Previous post was at 18:49 ----------

Just to clarify how a simple system would work: divide the VCO by 52, divide your reference by 5 - lock the two together (=2MHz in both cases).

Keith.

Ok, I was wrong about the multiplier/divider values, but the concept is still the same (I was off by a factor of 5, that's why I thought the PLL approach was infeasible.)

I am not sure what you mean by 'the concept is still the same'!

Anyway, the same principle I explained would be used if you wanted 104.01MHz from 10MHZ although I am not sure if the dividers in the ICS525 would be big enough for that - I would have to check.

Keith

"Just to clarify how a simple system would work: divide the VCO by 52, divide your reference by 5 - lock the two together (=2MHz in both case"

Yep, 52 and 5, or 104 and 10. Not sure why the OP is not getting the hint.

Thanks Keith and barry for your suggestion and clarifications....

Keith,

Aha, I hadn't even thought about putting a divider on the reference (10MHz) input; that makes everything work out. I must not have been paying attention in class that day.

Synthesizers can get quite complex but simplistically, if you are designing something for say a receiver with 12.5kHz channel spacing then you divide the reference down to 12.5kHz and the VCO to the same. Then every time you change the VCO divider by one you move one channel in the VCO frequency.

By the way, the ICS525 couldn't do 104.01MHz from 10MHz. It could do 104.1MHz with 24.6ppm error (i.e. it cannot do that exactly).

Keith.